FinFET device with a reduced width

Patent metadata

Field	Value
Publication number	US-10707331-B2
Application number	US-201715581206-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.

First claim

What is claimed is:

1. A method comprising:
forming a fin structure on a substrate;
forming a dummy gate wrapped around the fin structure;
depositing an interlayer dielectric (ILD) layer over the fin structure;
removing the dummy gate; and
after measuring a fin width of the fin structure and determining that the measured fin width exceeds a target fin width that defines a channel dimension for optimizing carrier mobility, wherein the target fin width exceeds a minimum fin width, performing an etching process on an exposed portion of the fin structure having the measured fin width to reduce a width of the exposed portion of the fin structure, such that the reduced fin width of the exposed portion of the fin structure is substantially the same as the target fin width after the performing of the etching process, wherein a difference between the reduced fin width and the minimum fin width is less than a difference between the measured fin width and the minimum fin width, wherein the fin structure is a first fin structure of a plurality of fin structures having a distribution of measured fin widths and reduced fin widths and wherein a distribution of the measured fin widths is wider than a distribution of the reduced fin widths.

2. The method of claim 1 , wherein the target fin width is a first target fin width, wherein the minimum fin width defines a fin width prone to cause a defective fin structure, and wherein the first target fin width is less than or equal to a second target fin width that defines a fin width that ensures sufficient structural strength of the fin structure during processing.

3. The method of claim 1 , further comprising, depositing a gate dielectric layer over the exposed portion of the fin structure and depositing a metal gate layer over the gate dielectric layer.

4. The method of claim 1 , wherein the etching process reduces the width of the exposed portion of the fin structure to a width that ranges from about 0.5 nm less than the target fin width to about 0.5 nm greater than the target fin width.

5. The method of claim 1 , further comprising applying the etching process for a period of time based in part on the measured fin width of the fin structure and the target fin width.

6. The method of claim 1 , wherein the measuring the fin width of the fin structure includes using a scanning electron microscope (SEM) or transmission electron microscopy (TEM).

7. The method of claim 1 , further comprising, before removing the dummy gate, forming source/drain regions within the fin structure, such that the dummy gate interposes the source/drain regions.

8. The method of claim 1 , wherein after the etching process, a width of a portion of the fin structure gradually increases from the reduced fin width of the exposed portion of the fin structure to the measured width of an unexposed portion of the fin structure.

9. The method of claim 1 , wherein the etching process is an isotropic etching process.

10. A method comprising:
forming a fin structure on a substrate;
forming a gate structure that includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate, wherein the gate structure is wrapped around a channel region of the fin structure;
forming epitaxial source/drain features in source/drain regions of the fin structure, wherein the gate structure interposes the epitaxial source/drain features;
forming an interlayer dielectric (ILD) layer over the fin structure, the gate structure, and the epitaxial source/drain features;
removing the dummy gate of the gate structure to expose the channel region of the fin structure;
when, before trimming the fin structure, a width of the fin structure is less than or equal to a threshold channel width, forming a metal gate over the exposed channel region of the fin structure without trimming the fin structure; and
when the width of the fin structure is greater than the threshold channel width, trimming a width of the channel region of the fin structure before forming the metal gate over the exposed channel region of the fin structure, such that the width of the channel region after trimming is less than or equal to the threshold channel width.

11. The method of claim 10 , further comprising measuring the width of the fin structure after forming the fin structure and before forming the gate structure.

12. The method of claim 10 , wherein the threshold channel width is less than a threshold fin width for providing mechanical strength during processing.

13. The method of claim 10 , wherein the trimming includes performing an oxidation process on the channel region of the fin structure to create an oxide material layer from outer portions of the channel region of the fin structure.

14. The method of claim 13 , further comprising, after performing the oxidation process, applying an etching process to remove the oxide material layer.

15. The method of claim 10 , wherein the trimming the width of the channel region of the fin structure includes removing less than or equal to about 5 nm from each side of the channel region of the fin structure.

16. The method of claim 10 , wherein the trimming includes performing a wet etching process.

17. The method of claim 10 , wherein gate spacers of the dummy gate structure remain after removing the dummy gate, such that a width of the fin structure underlying the gate spacers is not reduced.

18. A method for forming a semiconductor device comprising:
providing a substrate;
forming a fin structure having a first width on the substrate, wherein the first width ensures that the fin structure has sufficient mechanical strength for subsequent processing; and
when the first width is greater than a threshold channel width that optimizes carrier mobility in a channel region of the fin structure, performing a width reduction process on the channel region of the fin structure during a gate replacement process, such that source/drain regions of the fin structure have the first width and the channel region of the fin structure has a second width that is within a distribution range for the threshold channel width and greater than a minimum fin width, wherein a minimum width fin structure having the minimum fin width exceeds a tolerable risk of being defective, the channel region of the fin structure being disposed between the source/drain regions of the fin structure.

19. The method of claim 18 , wherein the minimum fin width is a first value, the threshold channel width is a second value greater than the first value, and the distribution range is ±0.5 nm of the threshold channel width.

20. The method of claim 18 , wherein the gate replacement process includes forming a gate dielectric over the channel region of the fin structure and forming a metal gate over the gate dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fung Ka-Hing
• Hsieh Chen-Yu
• Hsu Che-Yuan
• Wu Ming-Yuan
• Cheng Hsu-Chieh

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/238

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title