Template structure for quasi-monolithic die architectures

Patent metadata

Field	Value
Publication number	US-12550781-B2
Application number	US-202217891665-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

2 . The microelectronic assembly of claim 1 , wherein a material of the template structure includes silicon, aluminum and nitrogen, a ceramic, or a metal.

3 . The microelectronic assembly of claim 1 , wherein an overall thickness of the template structure is between 70 microns and 800 microns.

4 . The microelectronic assembly of claim 1 , wherein a depth of the cavity is between 20 microns and 45 microns.

5 . The microelectronic assembly of claim 1 , wherein the first surface of the template structure is coupled to the surface of the first die by fusion bonding.

6 . The microelectronic assembly of claim 1 , wherein the interconnects are first interconnects, and wherein the first surface of the template structure is coupled to the surface of the first die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

7 . The microelectronic assembly of claim 1 , wherein the second die includes lateral surfaces extending between the first and second surfaces, and the microelectronic assembly further comprising:
a fill material between the lateral surfaces of the second die and the template structure.

8 . The microelectronic assembly of claim 7 , wherein the fill material includes a conductive material.

9 . The microelectronic assembly of claim 1 , wherein the through-template opening includes a capillary underfill material with conductive fillers, an epoxy with conductive fillers, solder, a metal, or a polymer having conductive particles.

10 . The microelectronic assembly of claim 1 , wherein the surface of the first die is a second surface, and the first die further includes a first surface opposite the second surface and through-silicon vias (TSVs), and the microelectronic assembly further including:
a package substrate electrically coupled to the first surface of the first die by solder interconnects.

11 . A microelectronic assembly, comprising:
a first die having a surface; a first layer at the surface of the first die, the first layer including a second die electrically coupled to the surface of the first die by first interconnects having a pitch of less than 10 microns between adjacent first interconnects, and a first template structure on the surface of the first die and around the second die; and a second layer on the first layer, the second layer including a third die, a fourth die, and a second template structure, wherein the third die and the fourth die are electrically coupled to the second die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects, wherein the second template structure has a first surface coupled to the first layer and an opposing second surface and the second template structure includes a first cavity and a second cavity at the first surface, a first through-template opening extending from a top surface of the first cavity to the second surface of the second template structure, and a second through-template opening extending from a top surface of the second cavity to the second surface of the second template structure, and wherein the third die is within the first cavity and the fourth die is within the second cavity.

12 . The microelectronic assembly of claim 11 , wherein a material of the template structure includes silicon, aluminum and nitrogen, a ceramic, or a metal.

13 . The microelectronic assembly of claim 11 , wherein the second template structure further includes a fluidic channel.

14 . The microelectronic assembly of claim 13 , further comprising:
a fluid in the fluidic channel, wherein the fluid includes water, a fluorochemical liquid, silicone oil, ethylene glycol water, poly-alpha-olefin, silicate ester, helium, argon, or nitrogen.

15 . The microelectronic assembly of claim 11 , further comprising:
a heat sink at the second surface of the second template structure.

16 . The microelectronic assembly of claim 15 , further comprising:
a thermal interface material (TIM) between the heat sink and the second surface of the second template structure.

17 . A microelectronic assembly, comprising:
a first die having a surface; a plurality of second dies having a first surface and an opposing second surface, wherein the first surfaces of the plurality of second dies are at the surface of the first die, and wherein the plurality of second dies are electrically coupled to the first die by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a first template structure around and between the plurality of second dies; a plurality of third dies having a first surface and an opposing second surface, wherein the first surfaces of the plurality of third dies are at the second surfaces of the plurality of second dies, and wherein the plurality of third dies are electrically coupled to the plurality of second dies by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; a second template structure around and between the plurality of third dies, the second template structure having a first surface at the second surfaces of the plurality of second dies and an opposing second surface; and a substrate coupled to the second surface of the second template structure.

18 . The microelectronic assembly of claim 17 , wherein a material of the first and second template structures includes silicon, aluminum and nitrogen, a ceramic, or a metal.

19 . The microelectronic assembly of claim 17 , wherein a material of the substrate includes silicon.

20 . The microelectronic assembly of claim 17 , wherein a thickness of the substrate is between 50 microns and 800 microns.

Assignees

• Intel Corp

Inventors

• Karhade Omkar G
• Yoshihiro Tomita
• Elsherbini Adel A
• Krishnatreya Bhaskar Jyoti
• Talukdar Tushar
• Niazi Haris Khan
• Shi Yi
• Zhang Batao
• Li Wenhao
• Eid Feras

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title