Fan-out semiconductor package and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-10062652-B2
Application number	US-201615352100-A
Country	US
Kind code	B2
Filing date	Nov 15, 2016
Priority date	Mar 15, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a frame having a through hole, and including an upper surface, a lower surface opposing the upper surface, and an inner wall of the through hole connecting the upper surface and the lower surface;
a semiconductor chip disposed in the through hole, and having a first surface on which an electrode pad of the semiconductor chip is disposed and a second surface opposing the first surface;
a redistribution layer, on which the frame and the semiconductor chip are disposed, electrically connected to the electrode pads of the semiconductor chip, wherein the lower surface of the frame and the first surface of the semiconductor chip face the redistribution layer;
a first encapsulant disposed in a space between the frame and the semiconductor chip; and
a second encapsulant covering the upper surface of the frame, the second surface of the semiconductor chip, and the first encapsulant,
wherein the first encapsulant and the second encapsulant comprise different materials, and
the first encapsulant is in contact with a portion of the inner wall of the through hole, and the second encapsulant is in contact with another portion of the inner wall of the through hole.

2. The fan-out semiconductor package of claim 1 , wherein the second encapsulant is in contact with the upper surface of the frame.

3. The fan-out semiconductor package of claim 1 , wherein a modulus of elasticity of the first encapsulant is lower than a modulus of elasticity of the second encapsulant.

4. The fan-out semiconductor package of claim 1 , wherein a coefficient of thermal expansion of the first encapsulant is greater than a coefficient of thermal expansion of the second encapsulant.

5. The fan-out semiconductor package of claim 1 , wherein a glass transition temperature of the first encapsulant is greater than a glass transition temperature of the second encapsulant.

6. The fan-out semiconductor package of claim 1 , wherein a viscosity of a material for forming the first encapsulant is lower than a viscosity of a material for forming the second encapsulant.

7. The fan-out semiconductor package of claim 1 , wherein adhesive strength of the first encapsulant with respect to the semiconductor chip is greater than adhesive strength of the second encapsulant with respect to the semiconductor chip.

8. The fan-out semiconductor package of claim 1 , wherein the semiconductor chip comprises an integrated circuit.

9. The fan-out semiconductor package of claim 1 , further comprising:
a through wiring passing through the frame; and
wiring patterns disposed on the first and second surfaces of the frame, respectively.

10. The fan-out semiconductor package of claim 1 , further comprising:
a passivation layer disposed on one side of the redistribution layer, and having an opening; and
a connection terminal disposed in the opening,
wherein the connection terminal is electrically connected to the electrode pad of semiconductor chip through the redistribution layer.

11. The fan-out semiconductor package of claim 1 , wherein the second encapsulant comprises an opening.

12. The fan-out semiconductor package of claim 1 , further comprising a passivation layer covering the second encapsulant,
wherein the passivation layer comprises an opening opening a portion of the second encapsulant.

13. The fan-out semiconductor package of claim 1 , wherein the second encapsulant is in contact with the second surface of the semiconductor chip.

14. The fan-out semiconductor package of claim 1 , wherein the second encapsulant is in contact with the second surface of the semiconductor chip, the upper surface of the frame, and the first encapsulant.

15. A method of manufacturing a fan-out semiconductor package comprising:
preparing a frame having a through hole;
disposing a semiconductor chip in the through hole;
disposing a first encapsulant in a space between the frame and the semiconductor chip;
after disposing the first encapsulant in the space between the frame and the semiconductor chip, forming a second encapsulant to cover the frame, the first encapsulant, and the semiconductor chip; and
forming a redistribution layer on the frame and the semiconductor chip, the frame and the semiconductor chip disposed between the redistribution layer and the second encapsulant,
wherein the first encapsulant and the second encapsulant comprise different materials, and
the first encapsulant is in contact with a portion of the inner wall of the through hole, and the second encapsulant is in contact with another portion of the inner wall of the through hole.

16. The method of claim 15 , further comprising bonding a bonding film to the other side of the frame prior to the disposing the semiconductor chip,
wherein the semiconductor chip is bonded to the bonding film exposed by the through hole.

17. The method of claim 16 , further comprising removing the bonding film prior to the forming the redistribution layer,
wherein the redistribution layer is formed in a region from which the bonding film is removed.

18. The method of claim 15 , wherein the second encapsulant is in contact with the semiconductor chip, the frame, and the first encapsulant.

Assignees

• Samsung Electro Mech

Inventors

• Lee Ji Hyun
• Harr Kyoung Moo
• Kook Seung Yeop
• Kim Ji Hoon
• Ko Young Gwan

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W74/121 Primary

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title