Semiconductor device including semiconductor patterns having varied thicknesses

Patent metadata

Field	Value
Publication number	US-12550372-B2
Application number	US-202217694011-A
Country	US
Kind code	B2
Filing date	Mar 14, 2022
Priority date	Aug 5, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate that comprises a first region and a second region; a first active pattern in the first region, and a second active pattern in the second region; first source/drain patterns on the first active pattern, and a first channel pattern between the first source/drain patterns, the first channel pattern comprising a plurality of first semiconductor patterns that are stacked and spaced apart from each other; second source/drain patterns on the second active pattern, and a second channel pattern between the second source/drain patterns, the second channel pattern comprising a plurality of second semiconductor patterns that are stacked and spaced apart from each other; a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern; and a first gate dielectric layer between the first channel pattern and the first gate electrode, and a second gate dielectric layer between the second channel pattern and the second gate electrode, wherein the first gate dielectric layer comprises a first interface layer and a first high-k dielectric layer, wherein the second gate dielectric layer comprises a second interface layer and a second high-k dielectric layer, wherein a thickness of the first high-k dielectric layer is greater than a thickness of the second high-k dielectric layer, wherein the first interface layer comprises a dielectric material and the second interface layer comprises a dielectric material, and wherein an entire thickness of each of the first semiconductor patterns is less than an entire thickness of each of the second semiconductor patterns.

2 . The semiconductor device of claim 1 , wherein a width of the first gate electrode is greater than a width of the second gate electrode in a channel length direction.

3 . The semiconductor device of claim 1 , wherein a thickness of the first interface layer is substantially the same as a thickness of the second interface layer.

4 . The semiconductor device of claim 1 , wherein the first gate electrode comprises a plurality of first parts between the first semiconductor patterns that are vertically adjacent to each other,
wherein the second gate electrode comprises a plurality of second parts between the second semiconductor patterns that are vertically adjacent to each other, and wherein a thickness of each of the first parts is substantially the same as a thickness of each of the second parts.

5 . The semiconductor device of claim 4 , wherein a top surface of an uppermost one of the first parts is at a level substantially the same as a level of a top surface of an uppermost one of the second parts.

6 . The semiconductor device of claim 4 , wherein a vertical distance between the first parts that are adjacent to each other is substantially the same as a vertical distance between the second parts that are adjacent to each other.

7 . The semiconductor device of claim 1 , wherein a top surface of an uppermost one of the first semiconductor patterns is at a level lower than a level of a top surface of an uppermost one of the second semiconductor patterns.

8 . The semiconductor device of claim 1 , wherein a bottom surface of an uppermost one of the first semiconductor patterns is at a level higher than a level of a bottom surface of an uppermost one of the second semiconductor patterns.

9 . The semiconductor device of claim 1 , wherein a vertical distance between the first semiconductor patterns that are adjacent to each other is greater than a vertical distance between the second semiconductor patterns that are adjacent to each other.

10 . The semiconductor device of claim 1 , wherein the thickness of the first high-k dielectric layer is greater than a thickness of the first interface layer.

11 . A semiconductor device, comprising:
a substrate that includes a first region and a second region; a first active pattern in the first region, and a second active pattern in the second region; first source/drain patterns on the first active pattern, and a first channel pattern between the first source/drain patterns, the first channel pattern comprising a plurality of first semiconductor patterns that are stacked and spaced apart from each other; a pair of second source/drain patterns on the second active pattern, and a second channel pattern between the pair of second source/drain patterns, the second channel pattern comprising a plurality of second semiconductor patterns that are stacked and spaced apart from each other; and a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern, wherein a width of the first gate electrode is greater than a width of the second gate electrode in a channel length direction, and wherein an entire thickness of each of the first semiconductor patterns is less than an entire thickness of each of the second semiconductor patterns, wherein the first gate electrode comprises a plurality of first parts between the first semiconductor patterns that are vertically adjacent to each other, wherein the second gate electrode comprises a plurality of second parts between the second semiconductor patterns that are vertically adjacent to each other, and wherein a ratio of a thickness of each of the second parts to a thickness of each of the first parts is in a range of 0.9 to 1.1.

12 . The semiconductor device of claim 11 , further comprising:
a first gate dielectric layer between the first channel pattern and the first gate electrode; and a second gate dielectric layer between the second channel pattern and the second gate electrode, wherein the first gate dielectric layer comprises a first interface layer and a first high-k dielectric layer that are sequentially stacked, wherein the second gate dielectric layer comprises a second interface layer and a second high-k dielectric layer that are sequentially stacked, and wherein a thickness of the first high-k dielectric layer is greater than a thickness of the second high-k dielectric layer.

13 . The semiconductor device of claim 12 , wherein a thickness of the first interface layer is substantially the same as a thickness of the second interface layer.

14 . The semiconductor device of claim 11 , wherein a distance between the first active pattern and a top surface of an uppermost one of the first semiconductor patterns is less than a distance between the second active pattern and a top surface of an uppermost one of the second semiconductor patterns.

15 . The semiconductor device of claim 11 , wherein a vertical distance between the first parts that are adjacent to each other is substantially the same as a vertical distance between the second parts that are adjacent to each other.

16 . A semiconductor device, comprising:
a substrate that includes a first region and a second region; a first active pattern in the first region, and a second active pattern in the second region; first source/drain patterns on the first active pattern, and a first channel pattern between the first source/drain patterns, the first channel pattern comprising a plurality of first semiconductor patterns that are stacked and spaced apart from each other; second source/drain patterns on the second active pattern, and a second channel pattern between the second source/drain patterns, the second channel pattern comprising a plurality of second semiconductor patterns that are stacked and spaced apart from each other; a first gate electrode on the first channel pattern, and a second gate electrode on t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Doyoung
• Ha Daewon
• Kim Kyungho
• Kim Mingyu
• Hwang Kyuman

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title