Nanosheet semiconductor structure with inner spacer formed by oxidation

Patent metadata

Field	Value
Publication number	US-10615258-B2
Application number	US-201916285758-A
Country	US
Kind code	B2
Filing date	Feb 26, 2019
Priority date	Oct 11, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A semiconductor structure includes a nanosheet stack disposed on a base. The nanosheet stack includes one or more first nanosheet layers and one or more second nanosheet layers. Each of the one or more first nanosheet layers includes a first material and each of the one or more second nanosheet layers includes a second material different from the first material. Each of the one or more first nanosheet layers further includes outer portions of a third material converted from the first material. The outer portions are inner spacers.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a nanosheet stack disposed on a base, wherein the nanosheet stack comprises:
one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material;
wherein each of the one or more first nanosheet layers further comprises outer portions comprised of a third material converted from the first material; and
wherein the outer portions are inner spacers, wherein a length of the one or more second nanosheet layers exceeds a length of the one or more first nanosheet layers and the inner spacers.

2. The semiconductor structure of claim 1 , wherein the base comprises a substrate and a buffer disposed on the substrate.

3. The semiconductor structure of claim 2 , wherein the substrate is comprised of silicon, and the buffer is comprised of a III-V compound.

4. The semiconductor structure of claim 1 , wherein the inner spacers have a lateral thickness less than a lateral thickness of the first nanosheet layers, thereby causing the second nanosheet layers to extend beyond the inner spacers.

5. The semiconductor structure of claim 1 , wherein at least one of the first material and the second material is comprised of a III-V compound.

6. The semiconductor structure of claim 1 , wherein the first material is comprised of aluminum gallium arsenide, and wherein the second material is comprised of one of gallium arsenide and indium gallium arsenide.

7. The semiconductor structure of claim 6 , wherein the third material is comprised of aluminum oxide.

8. The semiconductor structure of claim 1 , further comprising a cladding spacer and a dummy gate disposed around a portion of the nanosheet stack and on the base.

9. The semiconductor structure of claim 1 , further comprising a cladding spacer and a replacement metal gate disposed around a portion of the nanosheet stack and on the base.

10. The semiconductor structure of claim 1 , further comprising at least one interlayer dielectric and at least one source/drain region disposed on the base.

11. The semiconductor structure of claim 10 , further comprising at least one contact within the at least one interlayer dielectric and in contact with the at least one source/drain region.

12. An integrated circuit comprising:
a nanosheet stack disposed on a base, wherein the nanosheet stack comprises:
one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material;
wherein each of the one or more first nanosheet layers further comprises outer portions comprised of a third material converted from the first material; and
wherein the outer portions are inner spacers, wherein a length of the one or more second nanosheet layers exceeds a length of the one or more first nanosheet layers and the inner spacers.

13. The integrated circuit of claim 12 , wherein the base comprises a substrate and a buffer disposed on the substrate.

14. The integrated circuit of claim 12 , wherein the inner spacers have a lateral thickness less than a lateral thickness of the first nanosheet layers, thereby causing the second nanosheet layers to extend beyond the inner spacers.

15. The integrated circuit of claim 12 , further comprising a cladding spacer and a replacement metal gate disposed around a portion of the nanosheet stack and on the base.

16. The integrated circuit of claim 12 , further comprising at least one interlayer dielectric and at least one source/drain region disposed on the base.

17. The integrated circuit of claim 16 , further comprising at least one contact within the at least one interlayer dielectric and in contact with the at least one source/drain region.

18. The integrated circuit of claim 12 , wherein the first material is comprised of aluminum gallium arsenide, and wherein the second material is comprised of one of gallium arsenide and indium gallium arsenide.

19. The semiconductor structure of claim 10 , wherein the at least one source/drain region is epitaxially grown.

20. The integrated circuit of claim 17 , wherein the at least one source/drain region is epitaxially grown.

Assignees

• IBM

Inventors

• Miao Xin
• Cheng Kangguo
• Zhang Chen
• Xu Wenyu

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3221

  Arsenides · CPC title

• H10P14/3218

  Phosphides · CPC title