Extra gate device for nanosheet

Patent metadata

Field	Value
Publication number	US-10515859-B2
Application number	US-201715624360-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Dec 30, 2015
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

First claim

The invention claimed is:

1. A method for forming semiconductor devices, comprising:
patterning a stack of alternating layers on a substrate over single gate (SG) regions and extra gate (EG) regions to form nanosheet structures, the alternating layers including alternating semiconductor and dielectric layers;
forming a dielectric material over sides of the nanosheet structures in EG regions, the dielectric material being disposed below a topmost semiconductor layer of the nanosheet structures in EG regions;
forming a spacer layer over side portions of the topmost semiconductor layer to protect the topmost semiconductor layer in EG regions;
removing the dielectric material;
etching away the dielectric layers and the semiconductor layers of the nanosheet structures for EG devices other than the topmost semiconductor layer; and
forming a gate structure in and over a dummy gate trench wherein the topmost semiconductor layer forms a device channel for the EG device.

2. The method as recited in claim 1 , wherein forming the gate structure includes:
depositing a first dielectric layer;
blocking one of the SG regions and the EG regions; and
adjusting a thickness of the first dielectric layer of the other of the SG regions and the EG regions that is unblocked.

3. The method as recited in claim 1 , wherein the nanosheet structures are formed over N wells and P wells to form P-type and N-type devices for SG devices and EG devices.

4. The method as recited in claim 1 , wherein the nanosheet structures are formed by epitaxially growing alternating layers of the Si and SiGe.

5. The method as recited in claim 1 , wherein the SG devices include thinner gate dielectric than EG devices.

6. The method as recited in claim 1 , wherein forming the gate structure includes forming an oxide on the topmost semiconductor layer and depositing a gate dielectric layer on the oxide.

7. The method as recited in claim 6 , further comprising forming a gate conductor on the gate dielectric layer.

8. The method as recited in claim 1 , further comprising removing the spacer layer on the side portions of the topmost semiconductor layer.

9. The method as recited in claim 8 , wherein removing the spacer layer includes etching a top portion of the substrate in the EG regions.

10. The method as recited in claim 1 , wherein the stack of alternating layers includes at least three semiconductor layers.

11. The method as recited in claim 1 , further comprising doping a surface of the substrate in exposed areas where the EG devices are formed to form a highly doped region.

12. A method for forming semiconductor devices, comprising:
patterning a hard mask and a stack of alternating layers on a substrate over single gate (SG) regions and extra gate (EG) regions to form nanosheet structures, the alternating layers including alternating semiconductor and dielectric layers;
forming a dielectric material over the hard mask and sides of the nanosheet structures in EG regions, the dielectric material being disposed below a topmost semiconductor layer of the nanosheet structures in EG regions;
forming a spacer layer over side portions of the topmost semiconductor layer to protect the topmost semiconductor layer in EG regions;
removing the dielectric material;
etching away the dielectric layers and the semiconductor layers of the nanosheet structures for EG devices other than the topmost semiconductor layer; and
forming a gate structure in and over a dummy gate trench wherein the topmost semiconductor layer forms a device channel for the EG device.

13. The method as recited in claim 12 , wherein forming the gate structure includes:
depositing a first dielectric layer;
blocking one of the SG regions and the EG regions; and
adjusting a thickness of the first dielectric layer of the other of the SG regions and the EG regions that is unblocked.

14. The method as recited in claim 12 , wherein the nanosheet structures are formed over N wells and P wells to form P-type and N-type devices for SG devices and EG devices.

15. The method as recited in claim 12 , wherein the nanosheet structures are formed by epitaxially growing alternating layers of the Si and SiGe.

16. The method as recited in claim 12 , wherein the SG devices include thinner gate dielectric than EG devices.

17. The method as recited in claim 12 , wherein forming the gate structure includes forming an oxide on the topmost semiconductor layer and depositing a gate dielectric layer on the oxide.

18. The method as recited in claim 17 , further comprising forming a gate conductor on the gate dielectric layer.

19. The method as recited in claim 12 , further comprising removing the spacer layer on the side portions of the topmost semiconductor layer.

20. The method as recited in claim 19 , wherein removing the spacer layer includes etching a top portion of the substrate in the EG regions.

Assignees

• IBM

Inventors

• Doris Bruce B
• Hook Terence B
• Wang Junli

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• Y10S977/938

  Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title

• H01L29/42368

  Electricity · mapped topic