Quadruple gate dielectric for gate-all-around transistors

Patent metadata

Field	Value
Publication number	US-10832960-B2
Application number	US-201916270149-A
Country	US
Kind code	B2
Filing date	Feb 7, 2019
Priority date	Feb 7, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices, depositing a first sacrificial capping layer over the plurality of FET devices, selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices, depositing a second sacrificial capping layer and an oxygen blocking layer, selectively removing the oxygen blocking layer from a second set of the plurality of FET devices, and performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.

First claim

The invention claimed is:

1. A method for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices, the method comprising:
forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices;
depositing a first sacrificial capping layer over the plurality of FET devices;
selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices;
depositing a second sacrificial capping layer and an oxygen blocking layer;
selectively removing the oxygen blocking layer from a second set of the plurality of FET devices; and
performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.

2. The method of claim 1 , wherein the alternate semiconductor layers of the plurality of FET devices are silicon (Si) layers.

3. The method of claim 1 , wherein the first sacrificial capping layer includes an oxygen-rich capping material.

4. The method of claim 1 , wherein the oxygen blocking layer includes amorphous silicon (a-Si).

5. The method of claim 1 , wherein the plurality of FET devices include a first FET device, a second FET device, a third FET device, and a fourth FET device.

6. The method of claim 5 , wherein the gate dielectric thicknesses of the first, second, third, and fourth FET devices are successively larger.

7. The method of claim 1 , wherein each of the plurality of FET devices attains a different gate dielectric thickness based on a different oxygen amount provided during the anneal.

8. The method of claim 1 , further comprising depositing a work function metal layer over the plurality of FET devices having the different gate dielectric thicknesses.

9. A method for constructing devices with different gate dielectric thicknesses, the method comprising:
forming a first nanosheet stack for a first device, a second nanosheet stack for a second device, a third nanosheet stack for a third device, and a fourth nanosheet stack for a fourth device;
removing sacrificial layers from the first, second, third, and fourth nanosheet stacks;
forming an interfacial dielectric around alternate semiconductor layers of the first, second, third, and fourth devices;
depositing a first sacrificial capping layer;
selectively removing the first sacrificial capping layer from the first and third devices;
depositing a second sacrificial capping layer and an oxygen blocking layer;
selectively removing the oxygen blocking layer from the third and fourth devices; and
performing an anneal to create different gate dielectric thicknesses for each of the first, second, third, and fourth devices.

10. The method of claim 9 , wherein the sacrificial layers of the first, second, third, and fourth nanosheet stacks are silicon germanium (SiGe) layers.

11. The method of claim 9 , wherein the first sacrificial capping layer includes an oxygen-rich capping material.

12. The method of claim 9 , wherein the oxygen blocking layer includes amorphous silicon (a-Si).

13. The method of claim 9 , wherein the gate dielectric thicknesses of the first, second, third, and fourth devices are successively larger.

14. The method of claim 9 , wherein each of the first, second, third, and fourth devices attains a different gate dielectric thickness based on a different oxygen amount provided during the anneal.

15. The method of claim 9 , further comprising depositing a work function metal layer over the first, second, third, and fourth devices each having a different gate dielectric thickness.

Assignees

• IBM

Inventors

• Zhang Jingyun
• Ando Takashi
• Lee Choonghyun

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title