Semiconductor device including work function adjusting metal gate structure

Patent metadata

Field	Value
Publication number	US-11282939-B2
Application number	US-201916269712-A
Country	US
Kind code	B2
Filing date	Feb 7, 2019
Priority date	Jun 12, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin type protrusion protruding from a substrate and including a protrusion portion protruding from a top surface of the fin type protrusion;
a multi-channel active pattern on the protrusion portion, the multi-channel active pattern comprising a first active pattern and a second active pattern spaced apart from the first active pattern on the first active pattern;
a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal;
a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer;
a gate electrode on the silicon nitride layer;
an inner spacer disposed at a position overlapping the first active pattern and the second active pattern between the first active pattern and the second active pattern, and at a position overlapping the fin type protrusion and the first active pattern between the protrusion portion and the first active pattern;
an outer spacer disposed on the second active pattern;
an interfacial layer formed along the multi-channel active pattern between the multi-channel active pattern and the high dielectric constant insulating layer;
a semiconductor pattern disposed on at least one side of the gate electrode; and
an interlayer insulating layer on the semiconductor pattern and in contact with at least one side of the outer spacer,
wherein an outer side wall of the inner spacer is substantially coplanar with an outer side wall of the outer spacer and an outer side wall of the multi-channel active pattern,
wherein a bottom surface of the interfacial layer contacts the protrusion portion,
wherein a bottom surface of the inner spacer contacts the protrusion portion,
wherein a width of a top surface of the protrusion portion in a first direction is substantially the same as a width of the first active pattern in the first direction,
wherein a thickness of the silicon nitride layer is less than a thickness of the high dielectric constant insulating layer,
wherein the gate electrode comprises a conductive nitride layer formed along the silicon nitride layer,
wherein the conductive nitride layer contacts the silicon nitride layer,
wherein the conductive nitride layer comprises a titanium nitride (TiN) layer and a titanium silicon nitride (TiSiN) layer stacked on each other, and
wherein a thickness of the TiN layer is different from a thickness of the TiSiN layer.

2. The semiconductor device of claim 1 , wherein the high dielectric constant insulating layer is in contact with the silicon nitride layer.

3. The semiconductor device of claim 1 , further comprising:
an insertion layer comprising an oxidized layer between the silicon nitride layer and the gate electrode.

4. The semiconductor device of claim 3 , wherein the insertion layer comprises silicon oxynitride.

5. The semiconductor device of claim 1 , wherein each of the first and second active patterns comprises at least one nanowire.

6. A semiconductor device comprising:
a fin type protrusion protruding from a substrate and including a protrusion portion protruding from a first surface of the fin type protrusion;
a multi-channel active pattern on the protrusion portion, the multi-channel active pattern comprising a first active pattern and a second active pattern spaced apart from the first active pattern on the first active pattern;
a gate insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the gate insulating layer comprises an interfacial layer and a high dielectric constant insulating layer;
a gate electrode structure on the gate insulating layer;
an inner spacer disposed at a position overlapping the first active pattern and the second active pattern between the first active pattern and the second active pattern, and at a position overlapping the fin type protrusion and the first active pattern between the protrusion portion and the first active pattern;
an outer spacer disposed on the second active pattern;
a semiconductor pattern disposed on at least one side of the gate electrode structure; and
an interlayer insulating layer on the semiconductor pattern and in contact with at least one side of the outer spacer,
wherein the interfacial layer is formed along the multi-channel active pattern between the multi-channel active pattern and the high dielectric constant insulating layer,
wherein an outer side wall of the inner spacer is substantially coplanar with an outer side wall of the outer spacer and an outer side wall of the multi-channel active pattern,
wherein a bottom surface of the interfacial layer contacts the protrusion portion,
wherein a bottom surface of the inner spacer contacts the protrusion portion,
wherein a width of a top surface of the protrusion portion in a first direction is substantially the same as a width of the first active pattern in the first direction,
wherein the gate electrode structure comprises a work function adjusting liner which is in contact with the high dielectric constant insulating layer of the gate insulating layer,
wherein a dielectric constant of the work function adjusting liner is less than a dielectric constant of the high dielectric constant insulating layer,
wherein a thickness of the work function adjusting liner is less than a thickness of the high dielectric constant insulating layer,
wherein the gate electrode structure further comprises a titanium silicon nitride (TiSiN) layer and a titanium nitride (TiN) layer stacked on each other,
wherein the TiN layer is formed along and contacts the work function adjusting liner, and
wherein a thickness of the TiN layer is different from a thickness of the TiSiN layer.

7. The semiconductor device of claim 6 , wherein the work function adjusting liner comprises a silicon nitride layer.

8. The semiconductor device of claim 6 , wherein the work function adjusting liner comprises a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

9. The semiconductor device of claim 6 , wherein the high dielectric constant insulating layer is an insulating layer containing a metal.

10. The semiconductor device of claim 6 , wherein the multi-channel active pattern comprises silicon, and
wherein the interfacial layer comprises silicon oxide.

11. A semiconductor device comprising:
a fin type protrusion protruding from a substrate and including a protrusion portion protruding from a first surface of the fin type protrusion;
a first nanowire on the protrusion portion;
a second nanowire spaced apart from the first nanowire on the first nanowire;
a gate insulating layer formed along a periphery of the first nanowire and a periphery of the second nanowire on the first nanowire and the second nanowire, wherein the gate insulating layer comprises a high dielectric constant insulating layer;
a silicon nitride layer formed along the periphery of the first nanowire and the periphery of the second nanowire on the gate insulating layer and being in contact with the gate insulating layer;
a gate electrode which comprises a conductive liner containing titanium on the silicon nitride layer, the conductive liner formed along the periphery of the first nanowire and the periphery of the second nanowire;
an inner spacer disposed at a position overlapping the first nanowire and the second nanowire between the first nanowire and the second nanowire, and at a position overlapping the fin type protrusion and the first nanowire between the protrusion portion and the first nanow

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Byoung Hoon
• Kim Wan Don
• Park Jong Ho
• Hyun Sang Jin

Classifications

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title