Vertical memory devices

Patent metadata

Field	Value
Publication number	US-12550329-B2
Application number	US-202418929113-A
Country	US
Kind code	B2
Filing date	Oct 28, 2024
Priority date	Aug 23, 2019
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor device includes a stack including gate layers and insulating layers alternately stacked along a first direction, channel structures located in an array region of the stack, a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction, a second staircase located at a second section in the connection region of the stack, and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction. The intermediate staircase includes intermediate group stair steps ascending in the second direction. The intermediate staircase has a first sidewall and a second sidewall in the second direction. The second sidewall is closer to the second staircase than the first sidewall. The second sidewall is parallel to the first direction. The intermediate group stair steps of the intermediate staircase face the first staircase.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stack including gate layers and insulating layers alternately stacked along a first direction; channel structures located in an array region of the stack; a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction; a second staircase located at a second section in the connection region of the stack; and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction, the intermediate staircase including intermediate group stair steps ascending in the second direction, wherein the intermediate staircase has a first sidewall and a second sidewall in the second direction, and the second sidewall is closer to the second staircase than the first sidewall; and wherein the second sidewall is parallel to the first direction, and the intermediate group stair steps of the intermediate staircase face the first staircase.

2 . The semiconductor device of claim 1 , wherein:
the first staircase is positioned over the second staircase in the first direction and includes first group stair steps descending in the second direction; and the second staircase includes second group stair steps descending in the second direction.

3 . The semiconductor device of claim 2 , wherein:
the first staircase further includes first division stair steps descending in a third direction and a fourth direction that are perpendicular to the second direction and the first direction and opposite to each other; the second staircase further includes second division stair steps descending in the third direction and the fourth direction; and the intermediate staircase further includes third division stair steps descending in the third direction and the fourth direction.

4 . The semiconductor device of claim 3 , wherein:
a height difference of two consecutive first group stair steps of the first group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the first section, and a height difference of two consecutive first division stair steps of the first division stair steps in the first direction is equal to a height of one pair of the gate layer and the insulating layer in the first section, the N being greater than one.

5 . The semiconductor device of claim 3 , wherein:
a height difference of two consecutive second group stair steps of the second group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the second section, and a height difference of two consecutive second division stair steps of the second division stair steps in the first direction is equal to a height of one pair of the gate layer and the insulating layer in the second section.

6 . The semiconductor device of claim 1 , wherein:
the intermediate staircase has a same height as the first staircase in the first direction and is positioned over the second staircase in the first direction.

7 . The semiconductor device of claim 1 , wherein a height difference of two consecutive intermediate group stair steps of the intermediate group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the first section.

8 . The semiconductor device of claim 1 , wherein the first section in the connection region of the stack and the second section in the connection region of the stack have a same number of gate layers.

9 . The semiconductor device of claim 1 , further comprising:
contact structures located on the first staircase and the second staircase but not located on the intermediate staircase.

10 . The semiconductor device of claim 9 , wherein the contact structures further comprises:
first contact structures located on the first staircase and connected to the gate layers at the first section in the connection region of the stack; and second contact structures located on the second staircase and connected to the gate layers at the second section in the connection region of the stack.

11 . A semiconductor device, comprising:
a stack including gate layers and insulating layers alternately stacked along a first direction; channel structures located in an array region of the stack; a first staircase located at a first section in a connection region of the stack, the connection region and the array region being arranged in a second direction perpendicular to the first direction, the first staircase including first group stair steps descending in the second direction; a second staircase located at a second section in the connection region of the stack; and a intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction, the intermediate staircase including intermediate group stair steps ascending in the second direction.

12 . The semiconductor device of claim 11 , wherein:
the first staircase is positioned over the second staircase in the first direction and includes first group stair steps descending in the second direction; and the second staircase includes second group stair steps descending in the second direction.

13 . The semiconductor device of claim 12 , wherein:
the first staircase further includes first division stair steps descending in a third direction and a fourth direction that are perpendicular to the second direction and the first direction and opposite to each other; the second staircase further includes second division stair steps descending in the third direction and the fourth direction; and the intermediate staircase further includes third division stair steps descending in the third direction and the fourth direction.

14 . The semiconductor device of claim 13 , wherein:
a height difference of two consecutive first group stair steps of the first group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the first section; a height difference of two consecutive first division stair steps of the first division stair steps in the first direction is equal to a height of one pair of the gate layer and the insulating layer in the first section, the N being greater than one; a height difference of two consecutive second group stair steps of the second group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the second section; and a height difference of two consecutive second division stair steps of the second division stair steps in the first direction is equal to a height of one pair of the gate layer and the insulating layer in the second section.

15 . The semiconductor device of claim 1 , wherein:
the intermediate staircase has a same height as the first staircase and is positioned over the second staircase in the first direction.

16 . The semiconductor device of claim 11 , wherein a height difference of two consecutive intermediate group stair steps of the intermediate group stair steps in the first direction is equal to a height of N pairs of the gate layers and the insulating layers in the first section.

17 . The semiconductor device of claim 1 , further comprises:
first contact structures located on the first staircase, the first contact structures being connected to the gate layers at the first section in th

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Zhong
• Zhou Wenxi
• Xia Zhiliang

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title