Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10049744-B2
Application number	US-201615383213-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Jan 8, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region;
a lower stack structure comprising a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure comprising a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction on the connection region, and the second direction being substantially perpendicular to the first direction; and
a plurality of intermediate stack structures vertically stacked on the lower stack structure, each of the plurality of intermediate stack structures comprising a plurality of intermediate electrodes vertically stacked on the substrate, and each of the plurality of intermediate stack structures comprising a third stair step structure extending in the second direction on the connection region,
wherein a slope of the first stair Step structure has a first inclination angle with respect to a top surface of the substrate,
wherein a slope of the second stair step structure has a second inclination angle with respect to the top surface of the substrate,
wherein the plurality of intermediate stack structures comprise a fourth stair step structure extending in the first direction on the connection region, and a slope of the fourth stair step structure has a third inclination angle with respect to the top surface of the substrate, and
wherein the third inclination angle is different from the first inclination angle, and the second inclination angle is substantially equal to the first inclination angle.

2. The 3D semiconductor memory device of claim 1 , wherein each of the plurality of lower electrodes comprises a lower pad region exposed by one of the plurality of lower electrodes disposed immediately thereon,
wherein each of the plurality of intermediate electrodes comprises an intermediate pad region exposed by one of the plurality of intermediate electrodes disposed immediately thereon, and
wherein a length of one of the lower pad regions in the first direction is greater than a length of one of the intermediate pad regions in the first direction.

3. The 3D semiconductor memory device of claim 2 , wherein surface areas of the intermediate pad regions are substantially equal to each other, and
wherein the intermediate pad regions of each of the plurality of intermediate stack structures are arranged in the second direction in a plan view.

4. The 3D semiconductor memory device of claim 2 , wherein surface areas of the lower pad regions decrease as a vertical distance from the substrate increases.

5. The 3D semiconductor memory device of claim 1 , wherein each of the plurality of lower electrodes and each of the plurality of intermediate electrodes comprises:
a plurality of electrode portions extending in the first direction on the cell array region, the plurality of electrode portions being spaced apart from each other in the second direction;
an electrode connection portion extending in the second direction on the connection region to horizontally connect the plurality of electrode portions to each other; and
a plurality of extension portions extending from the electrode connection portion in the first direction onto the connection region, the plurality of extension portions being spaced apart from each other in the second direction.

6. The 3D semiconductor memory device of claim 1 , further comprising:
an upper stack structure disposed on an uppermost one of the plurality of intermediate stack structures,
wherein the upper stack structure comprises a plurality of upper electrodes vertically stacked on the uppermost one of the plurality of intermediate stack structures, and
wherein the upper stack structure comprises a fifth stair step structure extending in the first direction on the connection region.

7. The 3D semiconductor memory device of claim 6 , further comprising:
an upper dummy stack structure horizontally spaced apart from the upper stack structure and disposed on the connection region,
wherein the upper dummy stack structure comprises a plurality of upper dummy electrodes vertically stacked, and
wherein the plurality of upper dummy electrodes comprise sidewalls vertically substantially aligned with a sidewall of the uppermost one of the plurality of intermediate stack structures.

8. The 3D semiconductor memory device of claim 7 , wherein the plurality of upper dummy electrodes have respective lengths in the first direction and respective widths in the second direction, and
wherein the lengths and the widths of the plurality of upper dummy electrodes decrease as a vertical distance from the substrate increases.

9. The 3D semiconductor memory device of claim 1 , further comprising:
a plurality of vertical channels vertically extending through the plurality of intermediate stack structures and the lower stack structure on the cell array region; and
a data storage layer disposed between each of the plurality of vertical channels and the plurality of lower electrodes and between each of the plurality of vertical channels and the plurality of intermediate electrodes.

10. The 3D semiconductor memory device of claim 1 , wherein a thickness of each step of the first stair step structure is different from a thickness of each step of the fourth stair step structure.

11. The 3D semiconductor memory device of claim 1 , wherein a thickness of each step of the second stair step structure is substantially equal to a thickness of each step of the third stair step structure.

12. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region;
an electrode structure extending from the cell array region onto the connection region in a first direction, the electrode structure comprising a lower stack structure comprising a plurality of lower electrodes vertically stacked on the substrate and a plurality of intermediate stack structures vertically stacked on the lower stack structure to comprise a stair step structure in the first direction;
an upper stack structure comprising a plurality of upper electrodes vertically stacked on the electrode structure; and
an upper dummy stack structure comprising a plurality of upper dummy electrodes which are horizontally spaced apart from the upper stack structure and are vertically stacked on the electrode structure.

13. The 3D semiconductor memory device of claim 12 , wherein each of the plurality of intermediate stack structures comprises a plurality of intermediate electrodes vertically stacked,
wherein the plurality of intermediate electrodes of each of the plurality of intermediate stack structures comprise an uppermost one of the plurality of intermediate electrodes and remaining ones of the plurality of intermediate electrodes that are between the substrate and the uppermost one of the plurality of intermediate electrodes,
wherein the plurality of lower electrodes comprises an uppermost one of the plurality of lower electrodes and remaining ones of the plurality of lower electrodes that are between the substrate and the uppermost one of the plurality of lower electrodes,
wherein each of the remaining ones of the plurality of lower electrodes comprises a lower pad region exposed by one of the plurality of lower electrodes disposed immediately thereon on the connection region,
wherein each of the remaining ones of the plurality of intermediate electrodes comprises an intermediate pad region exposed by one of the plurality of intermediate electrodes disposed immediately thereon o

Assignees

• Jeong Da Woon
• Lee Sung Hun
• Yun Seokjung
• Park Hyunmog
• Shin Joongshik
• Yoon Young Bae
• Samsung Electronics Co Ltd

Inventors

• Jeong Da Woon
• Lee Sung-Hun
• Yun Seokjung
• Park Hyunmog
• Shin Joongshik
• Yoon Young-Bae

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title