Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016268166-A1
Application number	US-201615002799-A
Country	US
Kind code	A1
Filing date	Jan 21, 2016
Priority date	Mar 12, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

In a method of manufacturing a semiconductor memory device, a stack is formed by alternately stacking an interlayer insulating layer and a first electrically conductive layer. In addition, an insulating layer, a charge accumulation layer, and a semiconductor layer are formed on a side wall of the stack. In addition, a metal layer having a first cutting pattern is formed on the stack. In addition, the stack and the metal layer are cut and divided along a first cutting pattern. The first cutting pattern is provided between a plurality of memory regions, the memory regions are provided for constructing the semiconductor memory device. In addition, the first cutting pattern includes a plurality of cuttings, the cuttings extending in a first direction and being spaced by a predetermined distance in a direction crossing the first direction.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, comprising:
alternately stacking an interlayer insulating layer and a first electrically conductive layer to form a stack; forming an insulating layer, a charge accumulation layer, and a semiconductor layer on a side wall of the stack; forming a metal layer having a first cutting pattern on the stack; and cutting and dividing the stack and the metal layer along the first cutting pattern, the first cutting pattern being provided between a plurality of memory regions provided for constructing the semiconductor memory device, and the first cutting pattern comprising a plurality of cuttings, the cuttings extending in a first direction and being spaced by a predetermined distance in a direction crossing the first direction.

2 . The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the first cutting pattern comprises a plurality of first cuttings, the first cuttings extending in direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line.

3 . The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the first cutting pattern comprises a plurality of second cuttings, the second cuttings extending in a direction perpendicular to a dicing line and being spaced by a predetermined distance along the dicing line.

4 . The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the first cutting pattern comprises, a plurality of first cuttings, the first cuttings extending in a direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line, and a plurality of second cuttings, the second cuttings extending in a direction perpendicular to the dicing line and being spaced by a predetermined distance along the dicing line.

5 . The method of manufacturing a semiconductor memory device according to claim 1 , wherein
in cutting the stack and the metal layer, the stack has a second cutting pattern, the second cutting pattern is provided between the memory regions, and the second cutting pattern comprises a plurality of cuttings, the cuttings extending in a second direction and being spaced by a predetermined distance in a direction crossing the second direction.

6 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the second direction is the same as the first direction.

7 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the second direction crosses the first direction.

8 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the first cutting pattern comprises a plurality of first cuttings, the first cuttings extending in a direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line.

9 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the first cutting pattern comprises a plurality of second cuttings, the second cuttings extending in a direction perpendicular to a dicing line and being spaced by a predetermined distance along the dicing line.

10 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the first cutting pattern comprises a plurality of first cuttings, the first cuttings extending in a direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line, and the first cutting pattern comprises a plurality of second cuttings, the second cuttings extending in a direction perpendicular to a dicing line and being spaced by a predetermined distance along the dicing line.

11 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the second cutting pattern comprises a plurality of third cuttings, the third cuttings extending in a direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line.

12 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the second cutting pattern comprises a plurality of fourth cuttings, the fourth cuttings extending in a direction perpendicular to a dicing line and being spaced by a predetermined distance along the dicing line.

13 . The method of manufacturing a semiconductor memory device according to claim 5 , wherein
the second cutting pattern comprises a plurality of third cuttings, the third cuttings extending in a direction parallel to a dicing line and being spaced by a predetermined distance in a direction perpendicular to the dicing line, and the second cutting pattern comprises a plurality of fourth cuttings, the fourth cuttings extending in a direction perpendicular to the dicing line and being spaced by a predetermined distance along the dicing line.

14 . A semiconductor memory device, comprising:
a stack having an alternately stacked interlayer insulating layer and first electrically conductive layer; a semiconductor layer opposed to the stack via an insulating layer and a charge accumulation layer; and a metal layer provided above the stack, a first remaining portion being provided in a side end portion of the metal layer, the first remaining portion comprising the same material as the metal layer, the first remaining portion being electrically independent from the metal layer.

15 . The semiconductor memory device according to claim 14 , wherein
a second remaining portion is provided in a side end portion of the first electrically conductive layer, the second remaining portion comprising the same material as the first electrically conductive layer, the second remaining portion being electrically independent from the first electrically conductive layer.

16 . The semiconductor memory device according to claim 14 , wherein
a plurality of cuttings are provided in a side end portion of the first electrically conductive layer, the cuttings being spaced by a predetermined distance along a side end of the first electrically conductive layer.

17 . A semiconductor memory device, comprising:
a stack having an alternately stacked interlayer insulating layer and first electrically conductive layer; a semiconductor layer opposed to the stack via an insulating layer and a charge accumulation layer; and a metal layer provided on the stack, a plurality of cuttings being provided in a side end portion of the metal layer, the cuttings being spaced by a predetermined distance along a side end of the metal layer.

18 . The semiconductor memory device according to claim 17 , wherein
a remaining portion is provided in a side end portion of the first electrically conductive layer, the remaining portion comprising the same material as the first electrically conductive layer, the remaining portion being electrically independent from the first electrically conductive layer.

19 . The semiconductor memory device according to claim 17 , wherein
a plurality of cuttings are provided in a side end portion of the first electrically conductive layer, the cuttings being spaced by a predetermined distance along a side end of the first electrically conductive layer.

20 . A semiconductor wafer having a semiconductor memory device, comprising:
a substrate, a stack disp

Assignees

• Toshiba Kk

Inventors

• Nakajima Hiroomi

Classifications

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L23/544

  Electricity · mapped topic