Vertical memory devices

Patent metadata

Field	Value
Publication number	US-12550322-B2
Application number	US-202318220073-A
Country	US
Kind code	B2
Filing date	Jul 10, 2023
Priority date	Dec 19, 2019
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

First claim

What is claimed is:

1 . A vertical memory device, comprising:
gate electrodes spaced apart from each other in a first direction on a substrate, the first direction perpendicular to an upper surface of the substrate, and the gate electrodes stacked in a staircase shape; a channel extending through the gate electrodes in the first direction; a first conductive through via extending through a conductive pad of a first gate electrode from among the gate electrodes and electrically connected to the conductive pad, the first gate electrode being at an uppermost level of the stacked staircase shape of gate electrodes, the first conductive through via extending through second gate electrodes from among the gate electrodes that are disposed under the first gate electrode; a second conductive through via at the same level as the first conductive through via, the second conductive through via extending through and insulated from each of the gate electrodes of the stacked staircase shape of gate electrodes, the second conductive through via being electrically connected to a lower wiring formed on the substrate; a common source plate (CSP) on the lower wiring, wherein the first conductive through via extends through the CSP; a plurality of first insulation structures between the first conductive through via and respective sidewalls of the second gate electrodes facing the first conductive through via, the plurality of first insulation structures electrically insulating the first conductive through via from the respective second gate electrodes; a plurality of second insulation structures between the second conductive through via and respective sidewalls of the gate electrodes facing the second conductive through via, the plurality of second insulation structures electrically insulating the second conductive through via from the respective gate electrodes, wherein the plurality of second insulation structures are respectively disposed at different levels, each level corresponding to a respective one of the gate electrodes, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and wherein the conductive pad is formed at an end portion in the second direction of the first gate electrode, and a portion of the conductive pad that is in direct contact with the first conductive through via has a thickness in the first direction greater than that of other portions of the first gate electrode.

2 . The vertical memory device of claim 1 , wherein the first conductive through via comprises:
a vertical portion extending in the first direction; and a protrusion portion protruding from the vertical portion m a horizontal direction parallel to the upper surface of the substrate, and wherein the protrusion portion contacts a sidewall of the conductive pad of the first gate electrode.

3 . The vertical memory device of claim 2 , wherein the first conductive through via further includes a slope portion on the vertical portion, the slope portion having a width that gradually increases from a bottom of the slope portion toward a top of the slope portion.

4 . The vertical memory device of claim 2 , wherein a distance from a sidewall of the vertical portion of the first conductive through via to the sidewall of the conductive pad of the first gate electrode facing the protrusion portion of the first conductive through via is equal to or less than distances from the sidewall of the vertical portion of the first conductive through via to the respective sidewalls of the second gate electrodes facing the first conductive through via.

5 . The vertical memory device of claim 1 , wherein each of the second plurality of insulation structures comprises:
an insulation pattern; and a spacer covering lower and upper surfaces of the insulation pattern.

6 . The vertical memory device of claim 5 , wherein the insulation pattern comprises an oxide, and the spacer comprises a nitride.

7 . The vertical memory device of claim 1 , further comprising a blocking pattern covering lower and upper surfaces of each of the gate electrodes,
wherein the blocking pattern is not formed on a sidewall of the conductive pad of the first gate electrode facing the first conductive through via, and is formed on each of the sidewalls of the respective second gate electrodes facing the first conductive through via.

8 . The vertical memory device of claim 7 , wherein the blocking pattern comprises a metal oxide.

9 . The vertical memory device of claim 1 , wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and
wherein conductive pads are respectively formed at an end portion in the second direction of each of the gate electrodes, and have a thickness in the first direction greater than that of other portions of each of the gate electrodes.

10 . The vertical memory device of claim 1 , further comprising a plurality of first conductive through vias spaced apart from each other in the second direction, the first conductive through via being one of the plurality of first conductive through vias.

11 . The vertical memory device of claim 1 , further comprising:
a lower circuit pattern electrically connected to the lower wiring; and an insulating interlayer on the substrate, the insulating interlayer covering the lower circuit pattern, wherein the common source plate (CSP) is disposed on the insulating interlayer, wherein the gate electrodes are formed on the CSP.

12 . The vertical memory device of claim 11 , wherein the first conductive through via further extends through an upper portion of the insulating interlayer, and is electrically connected to the lower circuit pattern.

13 . The vertical memory device of claim 11 , further comprising a third conductive through via at a same level as the first conductive through via, the third conductive through via not extending through the CSP and the gate electrodes, and the third conductive through via extending through an upper portion of the insulating interlayer to be electrically connected to the lower circuit pattern.

14 . The vertical memory device of claim 13 , wherein the second conductive through via further extends through the CSP and the upper portion of the insulating interlayer to be electrically connected to the lower circuit pattern.

15 . The vertical memory device of claim 14 , further comprising a silicon nitride layer between a sidewall of the second conductive through via and the respective sidewalls of the gate electrodes facing the second conductive through via.

16 . The vertical memory device of claim 14 , further comprising an upper wiring on the third conductive through via and electrically connected to the third conductive through via,
wherein no additional upper wiring is formed on each of the first and conductive through vias, and the upper wiring configured to apply electrical signals to each of the first and second conductive through vias.

17 . A vertical memory device, comprising:
gate electrodes spaced apart from each other in a first direction on first and second regions of a substrate, the substrate including the first and second regions and a third region, the first direction perpendicular to an upper surface of the substrate, and the gate electrodes having a staircase shape on the second region of the substrate; a channel extending through the gate electrodes in the first direction on the first region of the substrate; a first conductive through via extending through some of the gate electrodes on the seco

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Donghwan
• Son Younghwan
• Kwan Shinhwan
• Han Jeehoon

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title