Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10141326-B1
Application number	US-201815885328-A
Country	US
Kind code	B1
Filing date	Jan 31, 2018
Priority date	Sep 5, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A semiconductor memory device includes a peripheral circuit element provided over a lower substrate; an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element; a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and a plurality of transistors electrically coupling the gate lines to the peripheral circuit element. The transistors include a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction; a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and gate dielectric layers disposed between the vertical channels and the gate electrode.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a peripheral circuit element provided over a lower substrate;
an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element;
a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and
a plurality of transistors electrically coupling the gate lines to the peripheral circuit element,
the transistors comprising:
a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction;
a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and
gate dielectric layers disposed between the vertical channels and the gate electrode.

2. The semiconductor memory device according to claim 1 ,
wherein the gate lines extend at different lengths in the second direction to form a step area of the memory cell area, and
wherein the transistors are disposed to overlap with the step area of the memory cell area in the first direction.

3. The semiconductor memory device according to claim 2 , further comprising:
a plurality of pads disposed over corresponding step portions of the gate lines in the step area and which are electrically coupled to the gate lines, respectively; and
a plurality of first contacts extending from top ends of the vertical channels in the first direction, passing through the corresponding step portions and which are electrically coupled to the pads, respectively.

4. The semiconductor memory device according to claim 3 , wherein the pads are provided with different heights.

5. The semiconductor memory device according to claim 1 ,
wherein the peripheral circuit element includes a block decoder which is electrically coupled to the gate electrode, and
wherein the block decoder is disposed to overlap with the transistors in the first direction.

6. The semiconductor memory device according to claim 1 , further comprising:
a plurality of global row lines provided in the interlayer dielectric layer and coupled to bottom ends, respectively, of the vertical channels.

7. The semiconductor memory device according to claim 6 ,
wherein the peripheral circuit element includes a global line decoder which is electrically coupled to the global row lines, and
wherein the global line decoder is disposed to overlap with the transistors in the first direction.

8. The semiconductor memory device according to claim 1 , wherein the gate electrode has the same thickness as the upper substrate.

9. A semiconductor memory device comprising:
a peripheral circuit element provided over a lower substrate;
an upper substrate provided over an interlayer dielectric layer which covers the peripheral circuit element;
a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate, a plurality of gate lines which are stacked over the upper substrate to surround the channel structure and a bit line which is coupled to the channel structure; and
a transistor electrically coupling the bit line to the peripheral circuit element,
the transistor comprising:
a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction;
a vertical channel passing through the gate electrode in the first direction and electrically coupled to the bit line; and
a gate dielectric layer disposed between the vertical channel and the gate electrode.

10. The semiconductor memory device according to claim 9 , wherein the gate electrode has the same thickness as the upper substrate.

11. The semiconductor memory device according to claim 9 ,
wherein the memory cell array further includes:
a plurality of first dielectric layers disposed over and under the gate lines; and
a dielectric layer stack including a plurality of second dielectric layers and a plurality of third dielectric layers alternately stacked along the first direction over the upper substrate, and
wherein the gate electrode is disposed to overlap with the dielectric layer stack in the first direction.

12. The semiconductor memory device according to claim 11 , further comprising:
a sidewall protection layer disposed between the gate lines and the first dielectric layers and the dielectric layer stack, and surrounding an outer wall of the dielectric layer stack.

13. The semiconductor memory device according to claim 11 , further comprising:
a fifth contact extending from a top end of the vertical channel in the first direction, and passing through the dielectric layer stack; and
a sixth contact disposed over the fifth contact, and electrically coupling the fifth contact and the bit line.

14. The semiconductor memory device according to claim 13 , wherein the fifth contact has the same structure as the channel structure.

15. The semiconductor memory device according to claim 14 , wherein the fifth contact comprises:
a cell channel layer extending in the first direction; and
a cell gate dielectric layer surrounding an outer wall of the cell channel layer.

16. The semiconductor memory device according to claim 9 ,
wherein the peripheral circuit element includes a page buffer which is electrically coupled to the vertical channel, and
wherein the page buffer is disposed to overlap with the transistor in the first direction.

17. A semiconductor memory device comprising:
a peripheral circuit element provided over a lower substrate;
an interlayer dielectric layer formed over the lower substrate, and covering the peripheral circuit element;
an upper substrate provided over the interlayer dielectric layer;
a memory cell array stacked over the upper substrate; and
a transistor provided between the memory cell array and the peripheral circuit element,
the transistor comprising:
a gate electrode disposed at the same layer as the upper substrate, and disposed to overlap with the memory cell array in the first direction;
a vertical channel passing through the gate electrode in the first direction; and
a gate dielectric layer disposed between the vertical channel and the gate electrode,

wherein the upper substrate and the gate electrode are disposed in a planar manner over a top surface of the interlayer dielectric layer.

18. The semiconductor memory device according to claim 17 , wherein the transistor is disposed to overlap with the peripheral circuit element in the first direction.

19. The semiconductor memory device according to claim 17 ,
wherein the peripheral circuit element includes a block decoder which is electrically coupled to the gate electrode, and
wherein the block decoder is disposed to overlap with the transistor in the first direction.

20. The semiconductor memory device according to claim 17 ,
wherein the peripheral circuit element includes a page buffer which is electrically coupled to the vertical channel, and
wherein the page buffer is disposed to overlap with the transistor in the first direction.

Assignees

• Sk Hynix Inc

Inventors

• Oh Sung-Lae
• Kim Dong-Hyuk
• Sung Sang-Hyun
• Jung Seong-Hun
• Jung Soo-Nam

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11573 Primary

  Electricity · mapped topic