Integrated circuit device including vertical memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9991271-B2
Application number	US-201615345763-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Jun 9, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a stack of alternating interlayer insulating layers and conductive layers on a substrate, each of the conductive layers extending in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers;
an insulating plug in one of the conductive layers under one of the landing portions; and
a contact plug extending from an upper surface of the one of the landing portions.

2. The semiconductor device of claim 1 , wherein the contact plug covers the insulating plug.

3. The semiconductor device of claim 2 , wherein a diameter of the contact plug is greater than a diameter of the insulating plug.

4. The semiconductor device of claim 3 , wherein a longitudinal axis of the contact plug is aligned with a longitudinal axis of the insulating plug.

5. The semiconductor device of claim 2 , wherein the contact plug has a first portion and second portion, the first portion on the upper surface of the one of the landing portions, the second portion extending from the first portion, a diameter of the second portion being less than a diameter of the first portion, and the diameter of the second portion being greater than a diameter of a portion of the insulating plug, the portion of the insulating plug being a portion of the insulating plug adjoining the first portion of the contact plug.

6. The semiconductor device of claim 1 , wherein a longitudinal axis of the contact plug is aligned with a longitudinal axis of the insulating plug.

7. The semiconductor device of claim 1 , further comprising:
a plurality of contact plugs, each extending from an upper surface of a respective one of the landing portions.

8. The semiconductor device of claim 7 , further comprising:
more than one insulation plug, and each of the insulating plugs in a respective one of the conductive layers under a respective one of the plurality of contact plugs.

9. The semiconductor device of claim 7 , further comprising:
insulating sidewalls on sides of each of the plurality of contact plugs.

10. The semiconductor device of claim 7 , wherein each of the plurality of contact plugs has a first portion and second portion, the first portion on the upper surface of the respective one of the landing portions, the second portion extending from the first portion, and a diameter of the second portion being less than a diameter of the first portion.

11. The semiconductor device of claim 1 , further comprising:
a plurality of vertical channel structures penetrating into the stack.

12. The semiconductor device of claim 1 , further comprising:
a plurality of vertical channel structures penetrating trough the stack and into the substrate.

13. A semiconductor device, comprising:
a first insulating layer over a portion of a substrate;
a first gate electrode layer on the first insulating layer;
a second insulating layer on the first gate electrode layer;
a second gate electrode layer on the second insulating layer;
a first conductive contact plug extending from an upper surface of the first gate electrode layer;
a second conductive contact plug extending from an upper surface of the second gate electrode layer; and
an insulating plug disposed in the first gate, electrode layer, the insulating plug disposed under the second conductive contact plug, and a diameter of a portion of the insulating plug being less than a diameter of the second conductive contact plug.

14. The semiconductor device of claim 13 , wherein a longitudinal axis of the second conductive contact plug is aligned with a longitudinal axis of the insulating plug.

15. The semiconductor device of claim 13 , further comprising:
insulating sidewalls on sides of the first and second conductive contact plugs.

16. The semiconductor device of claim 13 , wherein the second conductive contact plug has a first portion and second portion, the first portion of the second conductive contact plug on, the upper surface of the second gate electrode layer, the second portion of the second conductive contact plug extending from the first portion of the second conductive contact plug, and a diameter of the second portion of the second conductive contact plug being less than a diameter of the first portion of the second conductive contact plug.

17. The semiconductor device of claim 16 , wherein the diameter of the second portion of the second conductive contact plug is greater than a diameter of the portion of the insulating plug, the portion of the insulating plug being a portion adjoining the first conductive contact plug.

18. The semiconductor device of claim 1 , wherein the insulating plug is further provided through the one of the landing portions.

19. The semiconductor device of claim 13 , wherein t insulating plug is further provided in the second gate electrode layer.

Assignees

• Kang Shin Hwan
• Son Young Hwan
• Eun Dong Seog
• Lee Chang Sup
• Jang Jae Hoon
• Samsung Electronics Co Ltd

Inventors

• Kang Shin-Hwan
• Son Young-Hwan
• Eun Dong-Seog
• Lee Chang-Sup
• Jang Jae-Hoon

Classifications

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title