Three-dimensional memory devices having through-stack contact via structures and method of making thereof

Patent metadata

Field	Value
Publication number	US-10192929-B2
Application number	US-201715468519-A
Country	US
Kind code	B2
Filing date	Mar 24, 2017
Priority date	Mar 24, 2017
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory structures vertically extending through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
conductive structures located between the substrate and the alternating stack; and
conductive via structures, wherein each conductive via structure contacts a top surface of a respective one of the electrically conductive layers and a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures,
wherein each conductive via structure comprises an upper conductive via portion located directly on, and over, the top surface of the respective one of the electrically conductive layers, and a lower conductive via portion located between a horizontal plane including the top surface of the respective one of the electrically conductive layers and a horizontal plane including the top surface of the respective one of the conductive structures; and
wherein:
each upper conductive via portion is laterally surrounded by a respective upper insulating spacer;
each lower conductive via portion is laterally surrounded by a respective lower insulating spacer; and
the upper and lower insulating spacers comprise a same dielectric material.

2. The three-dimensional memory device of claim 1 , wherein the upper conductive via portion has a greater width than the lower conductive via portion.

3. The three-dimensional memory device of claim 1 , wherein:
the electrically conductive layers are in a configuration that provides a contact region in which each electrically conductive layer that is not a bottommost electrically conductive layer has a lesser area than any underlying electrically conductive layer among the electrically conductive layers; and
each conductive via structure physically contacts the top surface of the respective one of the electrically conductive layers within a respective area in which none of the electrically conductive layers overlies the respective one of the electrically conductive layers.

4. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises a vertical bit line containing resistive random access memory device.

5. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device.

6. The three-dimensional memory device of claim 1 , wherein:
the conductive via structures comprise word line contact via structures;
the electrically conductive layers comprise word lines of the three dimensional memory device; and
the conductive via structures electrically connect each word line to a respective peripheral device of a driver circuit located below the alternating stack.

7. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory structures vertically extending through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
conductive structures located between the substrate and the alternating stack; and
conductive via structures, wherein each conductive via structure contacts a top surface of a respective one of the electrically conductive layers and a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures,
wherein each conductive via structure comprises:
a metallic liner including a first vertically extending portion overlying the top surface of the respective one of the electrically conductive layers, a horizontal portion physically contacting the top surface of the respective one of the electrically conductive layers, and a second vertically extending portion extending between the top surface of the respective one of the electrically conductive layers and the top surface of the respective one of the conductive structures; and
a conductive fill material portion comprising a first conductive fill material sub-portion overlying a horizontal plane including the top surface of the respective one of the electrically conductive layers and a second conductive fill material sub-portion underlying the horizontal plane including the top surface of the respective one of the electrically conductive layers.

8. The three-dimensional memory device of claim 7 , wherein an inner periphery of a physical contact area between the metallic liner and the top surface of the respective one of the electrically conductive layers is spaced from an outer periphery of the physical contact area by a uniform lateral distance.

9. The three-dimensional memory device of claim 7 , wherein:
the conductive via structures have top surfaces located within a first horizontal plane;
the conductive structures have top surfaces located within a second horizontal plane; and
the horizontal portions of the metallic liners are located at different levels among the contact via structures.

10. The three-dimensional memory device of claim 9 , further comprising a memory level dielectric material portion that contacts horizontal surfaces and sidewalls of the electrically conductive layers within the contact region, wherein each conductive via structure vertically extends at least from a topmost surface of the memory level dielectric material portion to the top surface of the respective one of the electrically conductive layers.

11. A method of forming a three-dimensional memory device, comprising:
forming conductive structures over a substrate;
forming an alternating stack of insulating layers and spacer material layers over the conductive structures, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming an array of memory structures through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
forming conductive via structures on the electrically conductive layers, wherein each conductive via structure is formed directly on a top surface of a respective one of the electrically conductive layers and directly on a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures;
patterning the spacer material layers to form a contact region in which each spacer material layer that is not a bottommost spacer material layer has a lesser area than any underlying spacer material layer within the spacer material layers, wherein the conductive via structures are formed on horizontal surfaces of the electrically conductive layers within the contact region;
forming a memory level dielectric material portion over the contact region, wherein each conductive via structure is formed through the memory level dielectric material portion;
forming upper contact via cavities through the memory level dielectric material portion by a first anisotropic etch process, wherein top surfa

Assignees

• Sandisk Technologies Llc

Inventors

• Mori Yoshio

Classifications

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H01L27/11553

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic