Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12538477-B2
Application number	US-202318117604-A
Country	US
Kind code	B2
Filing date	Mar 6, 2023
Priority date	Apr 29, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein: the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

2 . The semiconductor memory device as claimed in claim 1 , wherein the bottom surface of the first conductive pad is at substantially the same level as a top surface of the device isolation layer and a top surface of the semiconductor substrate.

3 . The semiconductor memory device as claimed in claim 1 , further comprising word line structures that extend in a first direction, intersect the active portion, and are buried in the semiconductor substrate,
wherein: each of the word line structures includes a word line, a gate capping pattern on the word line, and a gate insulating pattern between the semiconductor substrate and the word line, and the bottom surface of the first conductive pad is at substantially the same level as a top surface of the gate capping pattern.

4 . The semiconductor memory device as claimed in claim 1 , wherein a bottom surface of the first bit line contact spacer and a bottom surface of the second bit line contact spacer are at substantially the same level.

5 . The semiconductor memory device as claimed in claim 1 , wherein the bottom surface of the first conductive pad is in contact with a portion of a top surface of the device isolation layer.

6 . The semiconductor memory device as claimed in claim 1 , wherein the first bit line contact spacer and the second bit line contact spacer each has a bottom surface at a lower level than the bottom surface of the first conductive pad.

7 . The semiconductor memory device as claimed in claim 6 , wherein the bottom surface of the first bit line contact spacer and the bottom surface of the second bit line contact spacer are at different levels.

8 . A semiconductor memory device, comprising:
a semiconductor substrate; a device isolation layer defining active portions in the semiconductor substrate; first pad insulating patterns on the semiconductor substrate and between the active portions, in a plan view; a first conductive pad on the semiconductor substrate and between the first pad insulating patterns adjacent to each other in a first direction; second conductive pads on the semiconductor substrate and between the first conductive pad and the first pad insulating patterns; a bit line structure on the first conductive pad, extending in a second direction, and intersecting the active portions; a bit line contact pattern between the bit line structure and the first conductive pad; and buried contact patterns on the second conductive pads, wherein: the first conductive pad and the second conductive pad each have a flat bottom surface that are at substantially the same level, and the first conductive pad has a sidewall aligned with a sidewall of the bit line contact pattern.

9 . The semiconductor memory device as claimed in claim 8 , wherein:
a first sidewall of the first conductive pad is spaced apart from one of the second conductive pads by a first distance, a second sidewall of the first conductive pad is spaced apart from another of the second conductive pads by a second distance, and the second distance is different from the first distance.

10 . The semiconductor memory device as claimed in claim 8 , further comprising a word line structure that extends in the first direction, intersects the active portion, and is buried in the semiconductor substrate,
wherein: the word line structure includes a word line, a gate capping pattern on the word line, and a gate insulating pattern between the semiconductor substrate and the word line, and the bottom surface of the first conductive pad and the bottom surface of the second conductive pad are at substantially the same level as a top surface of the gate capping pattern.

11 . The semiconductor memory device as claimed in claim 10 , wherein the second conductive pads are between the active portions and the buried contact patterns at a side of the word line structure.

12 . The semiconductor memory device as claimed in claim 8 , wherein sidewalls of the second conductive pads are in contact with the first pad insulating patterns.

13 . The semiconductor memory device as claimed in claim 8 , wherein a thickness of the first conductive pad is less than thicknesses of the second conductive pads.

14 . The semiconductor memory device as claimed in claim 8 , further comprising bit line spacers covering sidewalls of the bit line structure,
wherein portions of the bit line spacers are between the first conductive pad and the second conductive pads.

15 . The semiconductor memory device as claimed in claim 8 , further comprising a bit line contact spacer covering the sidewall of the first conductive pad,
wherein a bottom surface of the bit line contact spacer is at a lower level than the bottom surface of the first conductive pad.

16 . The semiconductor memory device as claimed in claim 8 , further comprising second pad insulating patterns extending in the first direction on the semiconductor substrate,
wherein the first conductive pad is between the second pad insulating patterns adjacent to each other in the second direction.

17 . A semiconductor memory device, comprising:
a semiconductor substrate; a device isolation layer defining active portions in the semiconductor substrate; word line structures buried in the semiconductor substrate, extending in a first direction, and intersecting the active portions, each of the word line structures including a word line; a gate capping pattern on the word line; and a gate insulating pattern between the semiconductor substrate and the word line; first pad insulating patterns, each of which is on the semiconductor substrate and is between end portions of the active portions adjacent to each other in the first direction in a plan view; second pad insulating patterns extending in the first direction on the word line structures; a bit line structure intersecting the word line structures and extending in a second direction intersecting the first direction; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the bit line structure and the first conductive pad; second conductive pads on the semiconductor substrate and on end portions of the active portions; bit line spacers on sidewalls of the bit line structure; and buried contact patterns on the second conductive pads, wherein: the first conductive pad and the second conductive pad each have a flat bottom surface, the bottom surface of the first conductive pad and the bottom surface of the second conductive pad are each at substantially the same level as a top surface of the gate capping pattern, and the first conductive pad has a sidewall aligned with a sidewall of the bit line contact pattern and at le

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kiseok
• Ahn Junhyeok
• Kim Keunnam
• Yoon Chan-Sic
• Lee Myeong-Dong

Classifications

• H10B12/482

  Bit lines · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/02

  for one transistor one-capacitor [1T-1C] memory cells · CPC title

• H10B12/485 Primary

  Bit line contacts · CPC title