Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-10796950-B2
Application number	US-201916238172-A
Country	US
Kind code	B2
Filing date	Jan 2, 2019
Priority date	Nov 3, 2015
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a bit line and a bit-line capping pattern sequentially stacked on a semiconductor substrate;
forming a sacrificial spacer and a first spacer on sidewalls of the bit line and the bit-line capping pattern;
forming a contact plug to be in contact with the first spacer;
removing upper portions of the sacrificial spacer and the first spacer;
after removing the upper portions of the sacrificial spacer and the first spacer, forming a conductive layer to cover the sacrificial spacer, the first spacer and the bit-line capping pattern;
patterning the conductive layer to form landing pads;
exposing the sacrificial spacer between the landing pads;
removing the sacrificial spacer to form an air gap exposing a sidewall of the first spacer; and
forming an insulating pattern on the air gap and the first spacer.

2. The method of claim 1 , further comprising, before forming the contact plug:
forming a contact hole adjacent to the bit line; and
laterally enlarging a bottom portion of the contact hole to be laterally wider than an upper portion of the contact hole above the bottom portion.

3. The method of claim 2 , further comprising:
forming an interlayered insulating layer before forming the bit line and the bit-line capping pattern, the bit line disposed on the interlayered insulating layer,
wherein the forming of the contact hole comprises patterning the interlayered insulating layer to form an interlayered insulating pattern under the bit line, and
wherein the enlarging of the bottom portion of the contact hole includes removing a lateral portion of the interlayered insulating pattern.

4. The method of claim 1 , further comprising:
forming a barrier layer before forming the conductive layer; and
removing a portion of the barrier layer after patterning the conductive layer, wherein the removing the portion of the barrier layer is a separate step performed after completing patterning of the conductive layer.

5. The method of claim 4 , wherein the insulating pattern has a first bottom surface contacting an upper surface of the barrier layer and a second bottom surface exposed by the air gap, and the first bottom surface is positioned at a higher level than the second bottom surface.

6. The method of claim 1 , wherein the forming of the insulating pattern comprises:
a first deposition process of forming a first insulating layer to cover an upper region of the air gap; and
a second deposition process of forming a second insulating layer to fill a gap between the landing pads.

7. The method of claim 6 , wherein:
each of the first deposition process and the second deposition process uses silane-based gas and ammonia-based gas,
an amount of silane-based gas used in the first deposition process is greater than that in the second deposition process, and
an amount of ammonia-based gas used in the first deposition process is less than that in the second deposition process.

8. A method of fabricating a semiconductor device, comprising:
forming a bit line and a bit-line capping pattern sequentially stacked on a semiconductor substrate;
forming a sacrificial spacer and a first spacer on sidewalls of the bit line and the bit-line capping pattern;
forming a contact plug to be in contact with the first spacer;
removing upper portions of the sacrificial spacer and the first spacer;
forming a conductive layer to cover the sacrificial spacer, the first spacer and the bit-line capping pattern;
patterning the conductive layer to form landing pads;
exposing the sacrificial spacer between the landing pads;
removing the sacrificial spacer to form an air gap exposing a sidewall of the first spacer;
forming an insulating pattern on the air gap and the first spacer; and
forming a second spacer before forming the sacrificial spacer and the first spacer,
wherein the removing of the upper portions of the sacrificial spacer and the first spacer comprises exposing a sidewall of the second spacer, and
wherein an upper portion of second spacer is removed when the conductive layer is patterned.

9. A method of fabricating a semiconductor device, comprising:
forming a conductive line and a capping pattern sequentially stacked on a semiconductor substrate;
forming a sacrificial spacer and a first spacer on sidewalls of the conductive line and the capping pattern;
forming a contact plug to be in contact with the first spacer;
removing upper portions of the sacrificial spacer and the first spacer;
forming a conductive layer to cover the sacrificial spacer, the first spacer and the capping pattern;
patterning the conductive layer to form conductive pads;
exposing the sacrificial spacer between the conductive pads;
removing the sacrificial spacer to form an air gap exposing a sidewall of the first spacer;
forming a barrier layer before forming the conductive layer; and
removing a portion of the barrier layer after patterning the conductive layer wherein the removing the portion of the barrier layer is a separate step performed after completing patterning of the conductive layer.

10. The method of claim 9 , further comprising, before forming the contact plug:
forming a contact hole adjacent to the conductive line; and
laterally enlarging a bottom portion of the contact hole to be laterally wider than an upper portion of the contact hole above the bottom portion.

11. The method of claim 10 , further comprising:
forming an interlayered insulating layer before forming the conductive line and the capping pattern, the conductive line disposed on the interlayered insulating layer,
wherein the forming of the contact hole comprises patterning the interlayered insulating layer to form an interlayered insulating pattern under the conductive line, and
wherein the enlarging of the bottom portion of the contact hole includes removing a lateral portion of the interlayered insulating pattern.

12. The method of claim 9 , further comprising:
forming an insulating pattern on the air gap and the first spacer,
wherein the insulating pattern has a first bottom surface contacting an upper surface of the barrier layer and a second bottom surface exposed by the air gap, and the first bottom surface is positioned at a higher level than the second bottom surface.

13. The method of claim 12 , wherein the forming of the insulating pattern comprises:
a first deposition process of forming a first insulating layer to cover an upper region of the air gap; and
a second deposition process of forming a second insulating layer to fill a gap between the conductive pads.

14. The method of claim 13 , wherein:
each of the first deposition process and the second deposition process uses silane-based gas and ammonia-based gas,
an amount of silane-based gas used in the first deposition process is greater than that in the second deposition process, and
an amount of ammonia-based gas used in the first deposition process is less than that in the second deposition process.

15. The method of claim 9 , further comprising:
forming a second spacer before forming the sacrificial spacer and the first spacer,
wherein the removing of the upper portions of the sacrificial spacer and the first spacer comprises exposing a sidewall of the second spacer, and
wherein an upper portion of second spacer is removed when the conductive layer is patterned.

16. A method of fabricating a semiconductor device, comprising:
forming an interlayered insulating layer on a semiconductor substrate;
forming a conductive line and a capping patte

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Myeong-Dong
• Kim Keunnam
• Lee Dongryul
• Choi Minseong
• Choi Jimin
• Kim Yong Kwan
• Cho Changhyun
• Hwang Yoosang

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title