Semiconductor device

Patent metadata

Field	Value
Publication number	US-9613966-B2
Application number	US-201514697782-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Jun 27, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a plurality of active areas;
a bit line crossing the plurality of active areas;
a direct contact connecting a first active area of the plurality of active areas with the bit line;
an insulating spacer substantially covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate;
a contact pad connected with a side wall of a second active area of the plurality of active areas, the contact pad being next to the first active area;
a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad; and
a buried contact connected to the contact pad and filling the contact hole.

2. The semiconductor device of claim 1 , wherein a height of an upper surface of the contact pad is lower than a level of an upper surface of the plurality of active areas.

3. The semiconductor device of claim 1 , wherein the buried contact extends to a lower level than the level of the upper surface of the semiconductor substrate and is connected to the contact pad at a lower level than the level of the upper surface of the semiconductor substrate.

4. The semiconductor device of claim 1 , wherein the contact pad is in contact with the insulating spacer.

5. The semiconductor device of claim 1 , further comprising
a second insulating pattern defining on the bit line a landing pad hole in communication with the contact hole; and
a landing pad in the landing pad hole connected with the buried contact and vertically overlapping the bit line.

6. The semiconductor device of claim 5 , wherein the landing pad comprises a same material as the buried contact.

7. The semiconductor device of claim 1 , further comprising a capacitor lower electrode connected with the buried contact.

8. The semiconductor device of claim 1 , wherein the contact pad comprises an epitaxial semiconductor layer.

9. The semiconductor device of claim 1 , wherein the contact pad comprises a polycrystalline semiconductor layer.

10. The semiconductor device of claim 1 , wherein the contact pad comprises a conductive material doped with carbon.

11. The semiconductor device of claim 1 , wherein the contact pad comprises a metal.

12. The semiconductor device of claim 1 , further comprising a recess communicating with the contact hole and exposing the contact pad, and wherein the buried contact is connected with an inner wall of the recess.

13. The semiconductor device of claim 12 , further comprising a second contact pad contacting the inner wall of the recess, wherein the buried contact is connected with the second contact pad.

14. A semiconductor device comprising:
a semiconductor substrate having a plurality of active areas, the plurality of active areas including a first active area and a second active area;
a contact connecting the first active area with a bit line;
an insulating spacer at a side wall of the bit line;
a contact pad connected with a side wall of the second active area;
a contact hole exposing the insulating spacer and the contact pad; and
a buried contact connected to the contact pad and filling the contact hole, a contact area between the buried contact and at least one of the contact pad and the second active area extending over more than one side of the buried contact.

15. The semiconductor device of claim 14 , further comprising a first insulating pattern defining the contact hole.

16. The semiconductor device of claim 14 , wherein the insulating spacer substantially covers the side wall of the bit line and extends to a level lower than a level of an upper surface of the semiconductor substrate.

17. The semiconductor device of claim 14 , wherein the bit line crosses the plurality of active areas.

18. The semiconductor device of claim 14 , wherein the contact pad is next to the first active area.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dae-Ik
• Kim Hyoung-Sub
• Kim Sung-Eui

Classifications

• H01L27/10823

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L27/10855 Primary

  Electricity · mapped topic

• H01L27/10817

  Electricity · mapped topic