Semiconductor device

Patent metadata

Field	Value
Publication number	US-9761593-B2
Application number	US-201615214145-A
Country	US
Kind code	B2
Filing date	Jul 19, 2016
Priority date	Apr 14, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a device isolation layer in a substrate to define a plurality of active regions disposed proximal to an upper surface of the substrate;
forming a plurality of bit lines extending in a first direction on the substrate;
forming a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the upper surface of the substrate where the upper surface of the substrate is beneath both the upper surfaces of the first insulating lines and the upper surfaces of the bit lines;
forming a plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines, the plurality of first contact structures being connected to the plurality of active regions;
forming a plurality of second insulating lines extending in a third direction that is diagonal in relation to the second direction, the plurality of second insulating lines intersect the plurality of first insulating lines; and
wherein before forming the plurality of bit lines, forming a plurality of word lines buried in the substrate and a buried insulating layer that covers upper surfaces of the word lines at a same level as the upper surface of the substrate, wherein the plurality of first insulating lines overlap with the plurality of word lines.

2. The method of claim 1 , wherein the third direction is not perpendicular to the second direction.

3. The method of claim 1 , wherein forming the plurality of first insulating lines comprises:
forming an insulating material on the substrate, the insulating material has a upper surface of which a level are higher than those of upper surfaces of the a plurality of the bit lines and covers the upper surfaces a plurality of the bit lines;
etching a portion of the insulating material to define a space in which the plurality of the first insulating lines are formed;
forming the plurality of first insulating lines by filling the space defined by the insulating material with a constituent material of the first insulating lines, and
etching a remaining portion of the insulating material.

4. The method of claim 1 , further comprising forming a plurality of second contact structures disposed in an area isolated by the plurality of first insulating lines and the plurality of second insulating lines, the plurality of second contact structures are connected to the plurality of first contact structures
wherein one of the first contact structures is disposed to be connected to one of the second contact structures corresponding thereto.

5. The method of claim 4 , wherein forming the plurality of second insulating lines comprises:
forming an insulating material on the substrate, the insulating material has a upper surface of which a level are higher than those of upper surfaces of the a plurality of the bit lines and covers the upper surfaces the plurality of the hit lines and the first contact structures;
etching a portion of the insulating material to define a space in which the plurality of the second insulating lines are formed;
forming the plurality of second insulating lines by filling the space defined by the insulating material with a constituent material of the second insulating lines, and
etching a remaining portion of the insulating material.

6. The method of claim 4 , wherein the levels of upper surfaces of the plurality of first insulating lines are substantially equal to those of upper surfaces of the plurality of second insulating lines.

7. The method of claim 1 , further comprising, between forming the plurality of bit lines and forming the plurality of first insulating lines, forming an insulating spacer disposed at a sidewall of each of the plurality of bit lines,
wherein the insulating spacer is formed of a same material as the plurality of first insulating lines.

8. A method of manufacturing a semiconductor device, the method comprising:
forming a device isolation layer in a substrate to define a plurality of active regions disposed proximal to an upper surface of the substrate;
forming a plurality of bit lines extending in a first direction on the substrate;
forming a plurality of first insulating lines extending in a second direction that is different from the first direction and intersecting the plurality of bit line;
forming a plurality of first contact structures being defined by the plurality of bit lines and the plurality of first insulating lines;
forming a plurality of second insulating lines extending in a third direction that is diagonal in relation to the second direction and intersecting the plurality of first insulating line;
forming a plurality of second contact structures disposed in an area isolated by the plurality of first insulating lines and the plurality of second insulating lines, a horizontal section of each of the second contact structures has a parallelogram shape; and
wherein before forming the plurality of bit lines, forming a plurality of word lines buried in the substrate and a buried insulating layer that covers upper surfaces of the word lines at a same level as the upper surface of the substrate, wherein the plurality of first insulating lines overlap with the plurality of word lines.

9. The method of claim 8 , wherein the third direction is not perpendicular to the second direction and a horizontal section of each of the second contact structures has not a rectangular shape.

10. The method of claim 8 , wherein the second direction is perpendicular to the first direction and a horizontal section of each of the first contact structures has a rectangular shape.

11. The method of claim 10 , wherein the plurality of first contact structures are formed of a same material as the plurality of second contact structures.

12. The method of claim 8 , wherein the plurality of first contact structures each have a horizontal cross-sectional area having a first size, and the plurality of second contact structures each have a horizontal cross-sectional area having a second size that is larger than the first size.

13. The method of claim 8 , wherein the plurality of first contact structures connected to the plurality of active regions, and
wherein one of the first contact structures is disposed to be connected to one of the second contact structures corresponding thereto.

14. The method of claim 8 , wherein the plurality of first insulating lines have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and
wherein the levels of upper surfaces of the plurality of first insulating lines are substantially equal to those of upper surfaces of the plurality of second insulating lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Seok-Ho

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/76802

  Electricity · mapped topic

• H01L27/10885 Primary

  Electricity · mapped topic