Three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-12526996-B2
Application number	US-202218081172-A
Country	US
Kind code	B2
Filing date	Dec 14, 2022
Priority date	May 27, 2020
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures; a source contact above the memory stack and in contact with the semiconductor layer, wherein the source contact is electrically connected with the one of the channel structures, at least a portion of the source contact being buried within the semiconductor layer; and an interconnect layer disposed at a side of the memory stack where the source contact is located.

2 . The 3D memory device of claim 1 , wherein:
a material of the semiconductor plug is different from a material of the semiconductor layer.

3 . The 3D memory device of claim 1 , wherein:
a doping concentration of the semiconductor plug is different from a doping concentration of the semiconductor layer.

4 . The 3D memory device of claim 1 , wherein:
a top portion of the one of the channel structures is flush with or below a top surface of the semiconductor layer.

5 . The 3D memory device of claim 1 , further comprising:
a peripheral circuit on a substrate, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer and the source contact, the peripheral circuit and the interconnect layer disposed on the semiconductor layer are arranged at opposite sides of the memory stack.

6 . The 3D memory device of claim 5 , further comprising:
a bonding interface between the peripheral circuit and the plurality of channel structures, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, and the bonding interface.

7 . The 3D memory device of claim 6 , further comprising:
a peripheral contact extending vertically outside the memory stack and connected to the peripheral circuit, wherein: the peripheral contact extends through the semiconductor layer; and the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, the interconnect layer, the peripheral contact, and the bonding interface.

8 . The 3D memory device of claim 1 , wherein:
the one of the channel structures comprises a semiconductor channel; and a doping concentration of a top portion of the semiconductor channel surrounded by the semiconductor plug is different from a doping concentration of a remaining portion of the semiconductor channel.

9 . The 3D memory device of claim 1 , further comprising:
an insulating structure extending vertically through the memory stack and filled with at least one dielectric material.

10 . The 3D memory device of claim 1 , wherein:
the semiconductor layer comprises an N-type doped semiconductor layer or a P-type doped semiconductor layer.

11 . The 3D memory device of claim 1 , wherein:
the semiconductor layer is an N-type doped semiconductor layer; and the 3D memory device further comprises an insulating structure extending vertically through the memory stack, the N-type doped semiconductor layer being in contact with a dielectric material of the insulating structure.

12 . The 3D memory device of claim 1 , wherein:
the semiconductor layer is a P-type doped semiconductor layer, and the source contact is a first source contact; and the 3D memory device further comprises:
an N-well arranged in the P-type doped semiconductor layer; and
a second source contact extending into the N-well to have an electrical connection with the N-well.

13 . The 3D memory device of claim 12 , further comprising:
an insulating structure extending vertically through the memory stack, wherein the N-well is aligned with the insulating structure vertically.

14 . The 3D memory device of claim 12 , further comprising:
a peripheral circuit on a substrate; and a peripheral contact extending vertically outside the memory stack and connected with the peripheral circuit, wherein the N-well is electrically connected with the peripheral circuit through at least the second source contact, the interconnect layer, and the peripheral contact.

15 . A three-dimensional (3D) memory device, comprising:
a peripheral circuit; a memory stack arranged above the peripheral circuit and comprising interleaved conductive layers and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures; and a source contact above the memory stack and in contact with the semiconductor layer, wherein: the peripheral circuit is electrically connected with the one of the channel structures; and the peripheral circuit and an interconnect layer disposed on the semiconductor layer are arranged at opposite sides of the memory stack.

16 . The 3D memory device of claim 15 , wherein:
the peripheral circuit is arranged in a first semiconductor structure; and the memory stack is arranged in a second semiconductor structure, wherein: the first semiconductor structure and the second semiconductor structure are connected through a bonding interface; and the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, the semiconductor plug, and the bonding interface.

17 . The 3D memory device, of claim 15 , wherein:
the one of the channel structures comprises a semiconductor channel; and a doping concentration of a top portion of the semiconductor channel surrounded by the semiconductor plug is different from a doping concentration of a remaining portion of the semiconductor channel.

18 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit; a second semiconductor structure comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
a semiconductor layer above the memory stack;
a plurality of channel structures each extending vertically through the memory stack; and
a source contact arranged above the memory stack, a portion of the source contact being buried within the semiconductor layer, and another portion of the source contact being disposed outside the semiconductor layer toward a side opposite the memory stack; and
a bonding interface between the first semiconductor structure and the second semiconductor structure,
wherein:
the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer, the source contact, and the bonding interface; and
the peripheral circuit and the source contact are arranged at opposite sides of the memory stack.

19 . The 3D memory device of claim 18 , wherein:
an insulating structure extending vertically through the memory stack and filled with at least one dielectric material.

20 . The 3D memory device of claim 18 , further comprising:
an interconnect layer above the semiconductor layer, the other portion of the source contact being arranged into the interconnect layer, wherein the one

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B41/46

  with an inter-gate dielectric layer also being used as part of the peripheral transistor · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title