Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9704801-B1
Application number	US-201615268140-A
Country	US
Kind code	B1
Filing date	Sep 16, 2016
Priority date	Feb 17, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A semiconductor memory device includes first and second stacked bodies and a conductive body. The first and second stacked bodies are disposed side by side on the conductive layer. The conductive body is provided between the first and second stacked bodies. The first and second stacked bodies each includes a plurality of electrode layers stacked on the conductive layer, a first insulating layer between adjacent electrode layers, a second insulating layer including a first portion and a second portion, and a semiconductor layer extending through the plurality of electrode layers. The first portion is provided between the first insulating layer and one of the adjacent electrode layers. The second portion is separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body. The second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first stacked body provided on a conductive layer;
a second stacked body disposed side by side with the first stacked body on the conductive layer; and
a conductive body provided between the first stacked body and the second stacked body and electrically connected to the conductive layer,
the first stacked body and the second stacked body each including:
a plurality of electrode layers stacked on the conductive layer,
a first insulating layer provided between adjacent electrode layers of the plurality of electrode layers,
a second insulating layer including a first portion and a second portion, the first portion being provided between the first insulating layer and one of the adjacent electrode layers, the second portion being separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body, the second insulating layer having a dielectric constant higher than a dielectric constant of the first insulating layer,
a semiconductor layer extending through the plurality of electrode layers and the first insulating layer in a stacking direction of the plurality of electrode layers, and
a charge storage part provided between the semiconductor layer and at least one electrode layer of the plurality of electrode layers.

2. The semiconductor memory device according to claim 1 , further comprising:
a third insulating layer provided between the conductor body and the plurality of electrode layers and provided between the first insulating layer and the conductive body, the third insulating layer having a dielectric constant smaller than the dielectric constant of the second insulating layer,
the third insulating layer including a portion separating the second portion of the second insulating layer from the first portion of the second insulating layer.

3. The semiconductor memory device according to claim 2 , wherein the third insulating layer includes the same material as the first insulating layer.

4. The semiconductor memory device according to claim 1 , further comprising:
a plurality of first insulating layers provided between the plurality of electrode layers respectively, wherein
the plurality of electrode layers each includes a metal positioned between adjacent first insulating layers of the plurality of first insulating layers, and a barrier metal positioned between the metal and the first portion of the second insulating layer.

5. The semiconductor memory device according to claim 4 , wherein the metal positioned between the adjacent first insulating layers is a high-melting-point metal.

6. The semiconductor memory device according to claim 1 , wherein the adjacent electrode layers have an etching rate larger than an etching rate of the second insulating layer for a prescribed etchant.

7. The semiconductor memory device according to claim 1 , wherein the second insulating layer includes a High-k material.

8. The semiconductor memory device according to claim 1 , wherein the first portion of the second insulating layer is separated from the second portion at a corner where the end surface contacts a surface of the first insulating film facing the electrode layer.

9. The semiconductor memory device according to claim 1 , further comprising:
a fourth insulating layer provided on the first stacked body and the second stacked body and separated by the conductive body,
the fourth insulating layer having a dielectric constant smaller than the dielectric constant of the second insulating layer, and
the second insulating layer further including a third portion positioned between the fourth insulating layer and the conductive body.

10. The semiconductor memory device according to claim 1 , further comprising:
a fourth insulating layer provided on the first stacked body and the second stacked body and separated by the conductive body; and
a fifth insulating layer positioned between the fourth insulating layer and the conductive body, the fifth insulating layer having a dielectric constant higher than a dielectric constant of the fourth insulating layer.

11. The semiconductor memory device according to claim 10 , wherein the fifth insulating layer includes the same material as the second insulating layer.

12. The semiconductor memory device according to claim 1 , wherein
the conductive body includes a first portion and a second portion, the first portion including conductive polysilicon, and the second portion including a metal; and
the first portion is positioned between the conductive layer and the second portion.

13. A semiconductor memory device, comprising:
a first stacked body provided on a conductive layer;
a second stacked body disposed side by side with the first stacked body on the conductive layer;
a conductive body provided between the first stacked body and the second stacked body and electrically connected to the conductive layer; and
a first insulating layer provided on the first stacked body and the second stacked body and separated by an end portion of the conductive body,
the first stacked body and the second stacked body each including:
a plurality of electrode layers stacked on the conductive layer,
a semiconductor layer extending through the plurality of electrode layers in a first direction, the first direction being a stacking direction of the plurality of electrode layers, and
a charge storage part provided between the semiconductor layer and at least one electrode layer of the plurality of electrode layers,

the end portion of the conductive body having a width in a second direction wider than a width in the second direction of a portion of the conductive body positioned between the first stacked body and the second stacked body, the second direction being a direction from the first stacked body toward the second stacked body.

14. The semiconductor memory device according to claim 13 , further comprising:
a second insulating layer positioned between the first insulating layer and the end portion of the conductive body, the second insulating layer having a dielectric constant higher than a dielectric constant of the first insulating layer.

15. The semiconductor memory device according to claim 13 , wherein
the conductive body includes a first portion and a second portion, the first portion including conductive polysilicon, and the second portion including a metal;
the first portion is positioned between the conductive layer and the second portion; and
the second portion includes the end portion.

Assignees

• Toshiba Kk

Inventors

• Sonehara Takeshi
• Kito Masaru
• Nakamori Toshiya

Classifications

• H01L21/76816

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L23/528 Primary

  Electricity · mapped topic