Substrate-less lateral diode integrated circuit structures

Patent metadata

Field	Value
Publication number	US-12507475-B2
Application number	US-202117358329-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a single fin; a plurality of P-type epitaxial structures over and coupled to the single fin; a plurality of N-type epitaxial structures over and coupled to the single fin; and one or more spacings in locations over the single fin, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

2 . The integrated circuit structure of claim 1 , wherein the plurality of P-type epitaxial structures are coupled to ground, and the plurality of N-type epitaxial structures are coupled to one or more signal lines.

3 . The integrated circuit structure of claim 1 , wherein individual ones of the one or more spacings extend across a corresponding portion of a top surface of the single fin, the corresponding portion of the top surface of the single fin abutting the corresponding neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

4 . The integrated circuit structure of claim 1 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures, and wherein the N-type epitaxial structures are phosphorous-doped silicon structures.

5 . The integrated circuit structure of claim 1 , wherein the one or more spacings are one or more locations where a gate structure was removed or blocked from formation.

6 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a single fin;
a plurality of P-type epitaxial structures over and coupled to the single fin;
a plurality of N-type epitaxial structures over and coupled to the single fin; and
one or more spacings in locations over the single fin, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

7 . The computing device of claim 6 , further comprising:
a memory coupled to the board.

8 . The computing device of claim 6 , further comprising:
a communication chip coupled to the board.

9 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.

10 . The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

11 . An integrated circuit structure, comprising:
a stack of nanowires; a plurality of P-type epitaxial structures over the stack of nanowires; a plurality of N-type epitaxial structures over the stack of nanowires; and one or more spacings in locations over the stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

12 . The integrated circuit structure of claim 11 , wherein the plurality of P-type epitaxial structures are coupled to ground, and the plurality of N-type epitaxial structures are coupled to one or more signal lines.

13 . The integrated circuit structure of claim 11 , wherein individual ones of the one or more spacings extend across a corresponding portion of a top surface of an uppermost one of the stack of nanowires, the corresponding portion of the top surface of the uppermost one of the stack of nanowires abutting the corresponding neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

14 . The integrated circuit structure of claim 11 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures, and wherein the N-type epitaxial structures are phosphorous-doped silicon structures.

15 . The integrated circuit structure of claim 11 , wherein the one or more spacings are one or more locations where a gate structure was removed or blocked from formation.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a stack of nanowires;
a plurality of P-type epitaxial structures over the stack of nanowires;
a plurality of N-type epitaxial structures over the stack of nanowires;
and
one or more spacings in locations over the stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• THOMSON Nicholas
• Kolluru Kalyan
• Kar Ayan
• Ma Rui
• Orr Benjamin
• Jack Nathan
• Guha Biswajeet
• Greene Brian
• Hu Lin
• Lin Chung-Hsun

Classifications

• H10D89/611

  using diodes as protective elements · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/128

  Anode regions of diodes · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title