Semiconductor device and channel structure thereof

Patent metadata

Field	Value
Publication number	US-9425324-B2
Application number	US-201414501569-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along a channel direction of the semiconductor device and an outer sleeve layer disposed on the inner core strut. The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut and that comprises a two-dimensional (2-D) layered material, wherein the inner core strut mechanically supports the outer sleeve layer and wherein the outer sleeve layer has a central portion that defines a channel region and a pair of opposing end portions that respectively define source and drain regions.

2. The device of claim 1 , wherein the inner core strut defines a substantially uniform cross-sectional profile; wherein the outer sleeve layer substantially conformally wraps on the inner core strut; wherein the outer sleeve layer comprises one of a monolayer structure and a multilayer structure.

3. The device of claim 1 , wherein the outer sleeve layer fully wraps around the inner core strut.

4. The device claim 1 , wherein the outer sleeve layer partially wraps around the inner core strut and has an edge traversing along a channel length of the channel region thereof.

5. The device of claim 1 , wherein the outer sleeve layer further comprises a 2-D topological insulator material.

6. The device of claim 1 , further comprising a substrate having a planar surface, wherein the gate stack is substantially perpendicular with respect to the planar surface of the substrate.

7. The device of claim 1 , wherein the gate stack comprises a metal gate material and a high-k gate dielectric.

8. The device of claim 1 , further comprising a substrate having a planar surface, wherein the gate stack is substantially parallel with respect to the planar surface of the substrate.

9. The device of claim 8 , wherein the gate stack comprises a metal gate material and a high-k gate dielectric.

10. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut, wherein the inner core strut mechanically supports the outer sleeve layer; wherein a central portion of the outer sleeve layer defines a channel region; wherein a pair of opposing end portions of the outer sleeve layer respectively define source and drain regions.

11. The device of claim 10 , wherein the central portion of the outer sleeve layer is thinner than the opposing end portions thereof.

12. The device of claim 10 , further comprising a gate structure disposed on the outer sleeve layer at the channel region.

13. The device of claim 12 , wherein the gate structure comprises a metal gate material and a high-K gate dielectric.

14. The device of claim 10 , wherein the gate stack comprises a metal gate material and a high-k gate dielectric.

15. The device of claim 10 , further comprising a contact disposed on one of the end portions of the outer sleeve layer.

16. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut, wherein the inner core strut mechanically supports the outer sleeve layer and wherein the outer sleeve layer has a central portion that defines a channel region and a pair of opposing end portions that respectively define source and drain regions; and

a gate structure disposed on the outer sleeve layer at the channel region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Diaz Carlos H
• Colinge Jean-Pierre

Classifications

• H10D30/791

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title

• H10D62/213 Primary

  Channel regions of field-effect devices · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title