Stacked transistor architecture including nanowire or nanoribbon thin film transistors

Patent metadata

Field	Value
Publication number	US-2020105751-A1
Application number	US-201816145817-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

First claim

1 . An integrated circuit structure, comprising:
a first transistor structure including
a first nanowire or nanoribbon extending between a first source region and a first drain region;
a first gate electrode wrapped around the first nanowire or nanoribbon; and
a first gate dielectric between the first nanowire or nanoribbon and the first gate electrode; and
a second transistor structure above the first transistor structure and arranged in a stacked configuration with the first transistor structure, the second transistor structure including
a second nanowire or nanoribbon extending between a second source region and a second drain region;
a second gate electrode wrapped around the second nanowire or nanoribbon; and
a second gate dielectric between the second nanowire or nanoribbon and the second gate electrode;
wherein one or both of the first and second nanowire or nanoribbon includes a semiconducting oxide material.

2 . The integrated circuit structure of claim 1 , wherein both of the first and second nanowire or nanoribbon includes a semiconducting oxide material.

3 . The integrated circuit structure of claim 1 , wherein the second nanowire or nanoribbon is compositionally different from the first nanowire or nanoribbon.

4 . The integrated circuit structure of claim 1 , wherein the semiconducting oxide material comprises oxygen and at least one of nickel, indium, gallium, and zinc.

5 . (canceled)

6 . (canceled)

7 . (canceled)

8 . The integrated circuit structure of claim 1 , further comprising an insulator region between the first transistor structure and the second transistor structure.

9 . The integrated circuit structure of claim 8 , wherein the insulator region comprises an insulator material that is compositionally different from the first and second gate dielectrics.

10 . The integrated circuit structure of claim 1 , wherein the first nanowire or nanoribbon includes a crystalline semiconductor material, and the second nanowire or nanoribbon includes a semiconducting oxide material.

11 . The integrated circuit structure of claim 10 , wherein the first transistor structure is a p-type metal oxide semiconductor (PMOS) device, and the second transistor structure is an n-type metal oxide semiconductor (NMOS) device.

12 . The integrated circuit structure of claim 10 , wherein the crystalline semiconductor material comprises at least one of silicon and germanium, and the semiconducting oxide material comprises oxygen and at least one of indium, gallium, and zinc.

13 . The integrated circuit structure of claim 10 , wherein the crystalline semiconductor material comprises a group IV or group III-V semiconductor material.

14 . The integrated circuit structure of claim 1 , wherein the first nanowire or nanoribbon includes a first semiconducting oxide material, and the second nanowire or nanoribbon includes a second semiconducting oxide material.

15 . The integrated circuit structure of claim 14 , wherein the first transistor structure is a PMOS device, and the second transistor structure is an NMOS device.

16 . The integrated circuit structure of claim 14 , wherein the first transistor structure is an NMOS device, and the second transistor structure is a PMOS device.

17 . The integrated circuit structure of claim 1 , wherein the second nanowire or nanoribbon includes a crystalline semiconductor material, and the first nanowire or nanoribbon includes a semiconducting oxide material.

18 . The integrated circuit structure of claim 17 , wherein the second transistor structure is a PMOS device, and the first transistor structure is an NMOS device.

19 . The integrated circuit structure of claim 17 , wherein the crystalline semiconductor material comprises at least one of silicon and germanium, and the semiconducting oxide material comprises oxygen and at least one of indium, gallium, and zinc.

20 . The integrated circuit structure of claim 17 , wherein the crystalline semiconductor material comprises a group IV or group III-V semiconductor material.

21 . (canceled)

22 . The integrated circuit structure of claim 1 , wherein the first nanowire or nanoribbon is compositionally different from the first source and drain regions, and/or the second nanowire or nanoribbon is compositionally different from the second source and drain regions.

23 . (canceled)

24 . The integrated circuit structure of claim 1 , wherein the semiconducting oxide material includes indium, gallium, zinc, and oxygen.

25 . (canceled)

26 . An integrated circuit structure, comprising:
a first transistor structure including
a first nanowire or nanoribbon extending between a first source region and a first drain region, and including a crystalline semiconductor;
a first gate electrode wrapped around the first nanowire or nanoribbon; and
a first gate dielectric between the first nanowire or nanoribbon and the first gate electrode, and including a high-k dielectric material; and
a second transistor structure above the first transistor structure and arranged in a stacked configuration with the first transistor structure, the second transistor structure including
a second nanowire or nanoribbon extending between a second source region and a second drain region, and including a semiconducting oxide;
a second gate electrode wrapped around the second nanowire or nanoribbon; and
a second gate dielectric between the second nanowire or nanoribbon and the second gate electrode, and including a high-k dielectric material.

27 . (canceled)

28 . (canceled)

29 . (canceled)

30 . (canceled)

31 . The integrated circuit structure of claim 26 , wherein the crystalline semiconductor material comprises at least one of silicon and germanium, and the semiconducting oxide material comprises oxygen and at least one of indium, gallium, and zinc.

32 . (canceled)

33 . (canceled)

34 . The integrated circuit structure of claim 26 , wherein the first nanowire or nanoribbon is compositionally different from the first source and drain regions, and/or the second nanowire or nanoribbon is compositionally different from the second source and drain regions.

35 . An integrated circuit structure, comprising:
a first transistor structure including
a first nanowire or nanoribbon extending between a first source region and a first drain region, and including a first semiconducting oxide;
a first gate electrode wrapped around the first nanowire or nanoribbon; and
a first gate dielectric between the first nanowire or nanoribbon and the first gate electrode, and including a high-k dielectric material; and
a second transistor structure above the first transistor structure and arranged in a stacked configuration with the first transistor structure, the second transistor structure including
a second nanowire or nanoribbon extending between a second source region and a second drain region, and including a second semiconducting oxide;
a second gate electrode wrapped around the second nanowire or nanoribbon; and
a second gate dielectric between the second nanowire or nanoribbon and the second gate electrode, and including a high-k dielectric material.

36 . (canceled)

37 . (canceled)

Assignees

• Intel Corp

Inventors

• Dewey Gilbert
• Lilak Aaron
• Huang Cheng-Ying
• Kavalieros Jack
• Rachmady Willy
• Phan Anh
• Mannebach Ehren
• Sharma Abhishek
• Morrow Patrick
• Yoo Hui Jae

Classifications

• H01L27/0922 Primary

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic