Semiconductor devices having spacer structures

Patent metadata

Field	Value
Publication number	US-12490489-B2
Application number	US-202218072784-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Dec 3, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface of the gate dielectric layer; a gate electrode structure on the gate dielectric layer; a gate capping layer on the gate electrode structure; and a spacer structure on the substrate and covering the side surface of the gate dielectric layer and side surfaces of the gate electrode structure and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

2 . The semiconductor device as claimed in claim 1 , wherein the second spacer includes a protrusion protruding toward the gate dielectric layer, the protrusion being below the first spacer and covering the recess.

3 . The semiconductor device as claimed in claim 1 , wherein the gate dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, the recess being at a side surface of the first dielectric layer.

4 . The semiconductor device as claimed in claim 3 , wherein a horizontal length of the first dielectric layer is greater than a horizontal length of the second dielectric layer.

5 . The semiconductor device as claimed in claim 3 , wherein the first spacer covers a side surface of the second dielectric layer and the side surfaces of the gate electrode structure and the gate capping layer, the first spacer having a line shape extending in a vertical direction in a cross-sectional view.

6 . The semiconductor device as claimed in claim 5 , wherein a lower surface of the first spacer is at a same level as an upper surface of the first dielectric layer.

7 . The semiconductor device as claimed in claim 1 , wherein the second spacer and the third spacer have an L shape in a cross-sectional view.

8 . The semiconductor device as claimed in claim 1 , wherein a lower surface of the first spacer is at a higher level than a lower surface of the gate dielectric layer.

9 . The semiconductor device as claimed in claim 1 , wherein the spacer structure further includes a fourth spacer covering the third spacer, the fourth spacer including silicon oxide.

10 . The semiconductor device as claimed in claim 1 , further comprising a semiconductor layer between the substrate and the gate dielectric layer, the semiconductor layer including SiGe.

11 . The semiconductor device as claimed in claim 10 , wherein an upper surface of the semiconductor layer partially is in contact with a lower surface of the second spacer.

12 . The semiconductor device as claimed in claim 10 , wherein a thickness of a portion of the semiconductor layer not covered by the gate dielectric layer is smaller than a thickness of a portion of the semiconductor layer covered by the gate dielectric layer.

13 . The semiconductor device as claimed in claim 12 , wherein a lower surface of the second spacer is at a lower level than a lower surface of the gate dielectric layer.

14 . The semiconductor device as claimed in claim 12 , further comprising an etch stop layer covering the gate capping layer, the spacer structure, and a portion of the substrate, a lower surface of the etch stop layer being at a lower level than a lower surface of the gate dielectric layer.

15 . The semiconductor device as claimed in claim 1 , wherein a side surface of the second spacer is coplanar with a side surface of the first spacer, a void being defined between the second spacer and the recess.

16 . A semiconductor device, comprising:
a substrate including a cell area and a peripheral circuit area, the cell area having a first active region, and the peripheral circuit area having a second active region; a word line structure in the cell area of the substrate and extending in a first horizontal direction; a bit line structure extending in a second horizontal direction intersecting the first horizontal direction, the bit line structure crossing the word line structure; a capacitor structure electrically connected to the first active region, the capacitor structure including a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer; and a gate structure on the second active region in the peripheral circuit area, the gate structure including:
a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface of the gate dielectric layer,
a gate electrode structure on the gate dielectric layer,
a gate capping layer on the gate electrode structure, and
a spacer structure on the substrate and covering the side surface of the gate dielectric layer and side surfaces of the gate electrode structure and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

17 . The semiconductor device as claimed in claim 16 , further comprising:
a buried contact at a side surface of the bit line structure; a landing pad on the buried contact and contacting the lower electrode; and a first insulating structure at a side surface of the landing pad.

18 . The semiconductor device as claimed in claim 16 , further comprising:
an etch stop layer covering the gate structure; an interlayer insulating layer covering the etch stop layer; and a source/drain contact adjacent to the gate structure, the source/drain contact being in contact with the second active region and extending through the etch stop layer and the interlayer insulating layer.

19 . A semiconductor device, comprising:
a substrate including an active region and a source/drain region; a gate dielectric layer including a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer, the first dielectric layer including a recess at a side surface of the gate dielectric layer; a gate electrode structure on the gate dielectric layer; a gate capping layer on the gate electrode structure; a spacer structure on the substrate and covering the side surface of the gate dielectric layer and side surfaces of the gate electrode structure and the gate capping layer, the spacer structure including a first spacer, a second spacer covering the first spacer and the recess, a third spacer covering the second spacer, and a fourth spacer covering the third spacer, the second spacer and the third spacer including silicon nitride; an etch stop layer covering the gate capping layer and the spacer structure; an interlayer insulating layer covering the etch stop layer; and a source/drain contact contacting the source/drain region and extending through the interlayer insulating layer.

20 . The semiconductor device as claimed in claim 19 , wherein:
the first spacer covers a side surface of the second dielectric layer and the side surfaces of the gate electrode structure and the gate capping layer, the first spacer having a line shape extending in a vertical direction in a cross-sectional view; the second spacer is in contact with a side surface of the first spacer and an upper surface of the substrate, the second spacer having an L shape; and the third spacer covers the second spacer, the third spacer having an L shape.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeonil
• Kil Gyuhyun
• Back Doosan
• Yoon Chansic
• HAN Junghoon

Classifications

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title