Metal-oxide-semiconductor field-effect transistor with spacer over gate

Patent metadata

Field	Value
Publication number	US-10644130-B2
Application number	US-201213660728-A
Country	US
Kind code	B2
Filing date	Oct 25, 2012
Priority date	Oct 25, 2012
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.

First claim

What is claimed is:

1. A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:
forming a source and a drain in a substrate;
forming a conductive gate electrode over the substrate between the source and the drain;
forming a tetraethyl orthosilicate (TEOS) layer adjacent to a sidewall of the conductive gate electrode, wherein a portion of the TEOS layer extends laterally away from the conductive gate electrode;
forming an offset spacer adjacent to the TEOS layer and over the portion of the TEOS layer extending laterally away from the conductive gate electrode, wherein no implantation process is performed after forming the conductive gate electrode and before forming the offset spacer;
after forming the offset spacer, recessing the conductive gate electrode to expose a sidewall of the TEOS layer;
after recessing the conductive gate electrode, depositing a dielectric layer directly on the conductive gate electrode and over the offset spacer;
etching the dielectric layer to simultaneously form an outer spacer adjacent to the offset spacer and an inner spacer, the inner spacer at least partially over the conductive gate electrode; and
forming a lightly doped region disposed adjacent to the source in the substrate using the offset spacer as a mask.

2. The method of claim 1 , further comprising forming a gate dielectric between the substrate and the conductive gate electrode.

3. The method of claim 1 , wherein the conductive gate electrode comprises polysilicon.

4. The method of claim 1 , wherein the inner spacer and the outer spacer comprise silicon nitride or silicon dioxide.

5. The method of claim 1 , wherein the offset spacer comprises silicon nitride.

6. The method of claim 1 , further comprising forming at least a shallow trench isolation (STI) structure in the substrate prior to forming the source and the drain.

7. The method of claim 1 , wherein forming the source and the drain in the substrate comprises:
forming a sacrificial spacer adjacent the offset spacer;
performing an implantation process on the substrate using the sacrificial spacer as a mask; and
removing the sacrificial spacer.

8. A method comprising:
forming a gate stack over a substrate, the gate stack comprising a gate dielectric and a conductive gate electrode over the gate dielectric;
forming an L-shaped spacer on a sidewall of the gate stack, wherein no implantation process is performed after forming the gate stack and before forming the L-shaped spacer;
forming an offset spacer adjacent to the L-shaped spacer;
forming a sacrificial spacer adjacent the offset spacer;
performing an implantation process on the substrate using the gate stack, the L-shaped spacer, the offset spacer and the sacrificial spacer as an implantation mask;
removing the sacrificial spacer;
after removing the sacrificial spacer, recessing the conductive gate electrode below a topmost surface of the L-shaped spacer;
after recessing the conductive gate electrode, blanket depositing a dielectric layer over the gate stack, the L-shaped spacer and the offset spacer; and
etching the dielectric layer to simultaneously form an outer spacer adjacent to the offset spacer and an inner spacer over the gate stack.

9. The method of claim 8 , wherein the dielectric layer comprises silicon nitride or silicon dioxide.

10. The method of claim 8 , wherein the L-shaped spacer comprises tetraethyl orthosilicate (TEOS).

11. The method of claim 8 , wherein the offset spacer comprises silicon nitride.

12. The method of claim 8 , wherein the gate stack is a dummy gate stack.

13. The method of claim 12 , further comprising replacing the dummy gate stack with a metal gate stack.

14. The method of claim 8 , wherein the sacrificial spacer comprises silicon nitride or silicon dioxide.

15. A method comprising:
forming a gate stack over a substrate, the gate stack comprising a gate dielectric and a conductive gate electrode over the gate dielectric;
forming an L-shaped spacer on a sidewall of the gate stack, wherein no implantation process is performed after forming the gate stack and before forming the L-shaped spacer;
forming an offset spacer adjacent to the L-shaped spacer;
performing a first implantation process on the substrate using the gate stack, the L-shaped spacer and the offset spacer as an implantation mask to form a lightly doped region in the substrate;
after performing the first implantation process, forming a sacrificial spacer adjacent the offset spacer;
performing a second implantation process on the substrate using the gate stack, the L-shaped spacer, the offset spacer and the sacrificial spacer as an implantation mask to form a source/drain region;
removing the sacrificial spacer;
after removing the sacrificial spacer, etching the conductive gate electrode to expose a sidewall of the L-shaped spacer;
after recessing the gate stack, blanket depositing a dielectric layer over the gate stack, the L-shaped spacer and the offset spacer; and
etching the dielectric layer to simultaneously form an outer spacer adjacent to the offset spacer and an inner spacer over the conductive gate electrode, wherein the outer spacer is in physical contact with the lightly doped region.

16. The method of claim 15 , wherein the inner spacer partially covers a topmost surface of the conductive gate electrode.

17. The method of claim 15 , further comprising forming an isolation region in the substrate adjacent the source/drain region.

18. The method of claim 15 , wherein a bottommost surface of the L-shaped spacer is substantially level with a bottommost surface of the outer spacer.

19. The method of claim 15 , wherein the outer spacer is in physical contact with the source/drain region.

20. The method of claim 15 , wherein the inner spacer is in physical contact with the sidewall of the L-shaped spacer and a topmost surface of the conductive gate electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Chung-Yuan
• Wang Jen-Pan

Classifications

• H01L29/6656

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L29/6659 Primary

  Electricity · mapped topic