Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9355848-B2
Application number	US-201314057095-A
Country	US
Kind code	B2
Filing date	Oct 18, 2013
Priority date	Oct 18, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
forming a gate electrode layer on a substrate;
forming a spacer structure on a sidewall of the gate electrode layer;
forming a dielectric cap film to cover the gate electrode layer and the spacer structure;
performing a source/drain implantation to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation;
removing the dielectric cap film after the source/drain implantation; and
saliciding the gate electrode layer, wherein the dielectric cap film is removed before the saliciding step.

2. The method for forming the semiconductor structure according to claim 1 , wherein the saliciding step expands an upper portion of the gate electrode layer to form a pileus electrode portion wider than the gate electrode layer.

3. The method for forming the semiconductor structure according to claim 1 , wherein the saliciding step changes the gate electrode layer into a mushroom gate electrode having a stipe electrode portion and a pileus electrode portion on the stipe electrode portion.

4. The method for forming the semiconductor structure according to claim 3 , wherein a width of a part of the pileus electrode portion beyond a sidewall of the stipe electrode portion is between 5 Å and 20 Å.

5. The method for forming the semiconductor structure according to claim 1 , wherein a thickness of the dielectric cap film is between 20 Å and 50 Å.

6. The method for forming the semiconductor structure according to claim 1 , wherein the spacer structure serves as a mask for the source/drain implantation.

7. The method for forming the semiconductor structure according to claim 1 , wherein the spacer structure is formed by a method comprising:
forming a first spacer on the sidewall of the gate electrode layer; and
forming a second spacer on the first spacer.

8. The method for forming the semiconductor structure according to claim 7 , further comprising forming a lightly doped drain (LDD) in the substrate by an implantation step using the first spacer as a mask.

9. The method for forming the semiconductor structure according to claim 1 , further comprising:
forming a stress film covering the dielectric cap film; and
performing an annealing step to the substrate having the source/drain.

10. The method for forming the semiconductor structure according to claim 9 , further comprising removing the stress film after the annealing step.

Assignees

• United Microelectronics Corp

Inventors

• Chen Wei-Chih
• Tsai Chung-Hsien
• Chen Tung-Ming
• Chang Chih-Sheng
• Huang Jun-Chi
• Lin Chih-Jen
• Lin Yu-Hsiang

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/0131 Primary

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title