Methods for fabricating integrated circuits with improved implantation processes

Patent metadata

Field	Value
Publication number	US-9312189-B2
Application number	US-201414244651-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Apr 3, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate with first gates overlying second conductive type regions in the semiconductor substrate and second gates overlying first conductive type regions in the semiconductor substrate;
performing a first ion implantation to form halo implant regions in the semiconductor substrate adjacent selected second gates;
after performing the first ion implantation, performing a second ion implantation to form halo implant regions in the semiconductor substrate adjacent selected first gates;
after performing the second ion implantation, performing a third ion implantation to form extension implant regions in the semiconductor substrate adjacent the selected first gates; and
after performing the third ion implantation, performing a fourth ion implantation to form extension implant regions in the semiconductor substrate adjacent the selected second gates.

2. The method of claim 1 further comprising annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the selected first gates by performing a laser anneal process before performing the fourth ion implantation.

3. The method of claim 1 wherein:
performing the first ion implantation comprises forming a first patterned mask overlying the semiconductor substrate;
performing the second ion implantation comprises forming a second patterned mask overlying the semiconductor substrate;
performing the fourth ion implantation comprises forming a third patterned mask overlying the semiconductor substrate; and
the method further comprises:
removing the first patterned mask before performing the second ion implantation;
removing the second patterned mask before performing the fourth ion implantation.

4. The method of claim 1 wherein each ion implantation is performed with an implant angle of approximately 0° to approximately 30°, to an implant depth of approximately 5 nm to approximately 42 nm; by implanting ions selected from a group consisting essentially of B+, BF2+, In+, Ga+, As+, Sb+, P+, Ge, N and F; at an energy in the range of about 3 KeV to about 30 KeV.

5. The method of claim 1 further comprising:
forming first spacers around the first gates and the second gates before performing the first ion implantation and the second ion implantation; and
forming second spacers around the first gates and the second gates after performing the fourth ion implantation.

6. The method of claim 5 further comprising performing a deep ion implantation in the semiconductor substrate adjacent the second spacers to form source/drain implant regions in the semiconductor substrate.

7. The method of claim 6 further comprising annealing the source/drain implant regions in the semiconductor substrate by performing a laser anneal process.

8. The method of claim 7 further comprising annealing the semiconductor substrate using a rapid thermal anneal (RTA) process to form an n-type field effect transistor and a p-type field effect transistor on the semiconductor substrate.

9. A method for fabricating an integrated circuit, the method comprising:
providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate;
performing an initial portion of a series of ion implantations to form an initial layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack;
performing a series of ion implantations to form a layer of pocket implants in the semiconductor substrate adjacent the p-channel gate stack;
annealing the layer of pocket implants in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process; and
performing a final portion of a series of ion implantations to form a final layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack.

10. The method of claim 9 further comprising:
forming first spacers around the n-channel gate stack and the p-channel gate stack before performing an initial portion of a series of ion implantations to form an initial layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack; and
forming second spacers around the n-channel gate stack and the p-channel gate stack after performing a final portion of a series of ion implantations to form a final layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack.

11. The method of claim 10 further comprising performing deep source/drain ion implantations to form source/drain implant regions in the semiconductor substrate adjacent the second spacers around the n-channel gate stack and to form source/drain implant regions in the semiconductor substrate adjacent the second spacers around the p-channel gate stack.

12. The method of claim 11 further comprising:
annealing the source/drain implant regions in the semiconductor substrate by performing a laser anneal process; and
annealing the structure using a rapid thermal anneal (RTA) process to form an n-type field effect transistor and a p-type field effect transistor on the semiconductor substrate.

13. The method of claim 1 wherein:
providing the semiconductor substrate comprises providing the semiconductor substrate with first gates overlying n-type regions and second gates overlying p-type regions;
performing the first ion implantation to form the halo implant regions in the semiconductor substrate adjacent the selected second gates comprises implanting p-type dopants in the n-type regions;
performing the second ion implantation to form the halo implant regions in the semiconductor substrate adjacent the selected first gates comprises implanting n-type dopants in the p-type regions;
performing the third ion implantation to form the extension implant regions in the semiconductor substrate adjacent the selected first gates comprises implanting p-type dopants in the p-type regions; and
performing the fourth ion implantation to form the extension implant regions in the semiconductor substrate adjacent the selected second gates comprises implanting n-type dopants in the n-type regions.

14. The method of claim 13 further comprising:
after performing the fourth ion implantation, performing deep ion implantations to form deep source/drain regions in the p-type regions and deep source/drain regions in the n-type regions.

15. The method of claim 9 wherein:
performing the initial portion of a series of ion implantations to form the initial layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack comprises implanting p-type dopants;
performing the series of ion implantations to form the layer of pocket implants in the semiconductor substrate adjacent the p-channel gate stack comprises implanting n-type dopants and p-type dopants; and
performing the final portion of a series of ion implantations to form the final layer of pocket implants in the semiconductor substrate adjacent the n-channel gate stack comprises implanting n-type dopants.

Assignees

• Globalfoundries Inc

Inventors

• Zaka Alban
• Yan Ran
• Bazizi El Mehdi
• Hoentschel Jan

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title