Computer system using 3D OS NAND

Patent metadata

Field	Value
Publication number	US-12475948-B2
Application number	US-202017773887-A
Country	US
Kind code	B2
Filing date	Nov 9, 2020
Priority date	Nov 22, 2019
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.

First claim

The invention claimed is:

1 . A computer system comprising a computer node,
wherein the computer node comprises:
a central arithmetic processing unit comprising a central arithmetic processor and a register;
a cache memory configured to transfer data to the register and store data of the register; and
a three-dimensional NAND memory device configured to transfer data to the cache memory and to store data in the cache memory,
wherein the central arithmetic processor is configured to perform arithmetic operation using data in the register, wherein the three-dimensional NAND memory device comprises a transistor comprising a metal oxide in a channel formation region, and wherein the computer node does not comprise a DRAM.

2 . The computer system according to claim 1 , wherein the three-dimensional NAND memory device has a vertical NAND string.

3 . The computer system according to claim 1 ,
wherein the cache memory comprises an SRAM, wherein the cache memory is configured to store a temporary result of arithmetic operation, wherein the three-dimensional NAND memory device comprises a first memory region configured to store a program used in the arithmetic operation and a second memory region configured to store data to be retained even when power is off, and wherein the temporary result is configured to be transferred from the cache memory to the three-dimensional NAND memory device.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Ikeda Takayuki
• Kunitake Hitoshi

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• G06F1/32

  Means for saving power · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title