Apparatus and electronic devices including transistors comprising two-dimensional materials
US-2024339543-A1 · Oct 10, 2024 · US
US9634097B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9634097-B2 |
| Application number | US-201414552964-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 25, 2014 |
| Priority date | Nov 25, 2014 |
| Publication date | Apr 25, 2017 |
| Grant date | Apr 25, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.
Opening claim text (preview).
What is claimed is: 1. A three-dimensional (3D) non-volatile storage device, comprising: a substrate; a plurality of conductive layers above the substrate; a plurality of insulator layers alternating with the conductive layers in a stack above the substrate; and a three-dimensional memory array comprising a plurality of vertically-oriented NAND strings extending through the conductive layers and insulator layers above the substrate, each vertically-oriented NAND string comprising a plurality of non-volatile storage elements and a vertically-oriented cylindrically shaped channel, the vertically-oriented cylindrically shaped channel comprising an oxide semiconductor having a crystalline structure, the crystalline structure having an axis that is aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. 2. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the channel extends in a vertical direction, wherein the axis of the crystalline structure that is aligned with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel is aligned parallel to the vertical direction. 3. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the vertically-oriented cylindrically shaped channel has a cylindrical surface that is adjacent to the plurality of non-volatile storage elements, wherein the axis of the crystalline structure that is aligned with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel is aligned perpendicular to the cylindrical surface. 4. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the cylindrical shape of the channel comprises a plurality of concentric cylindrical layers, the crystalline structure comprising a plurality of crystalline layers, wherein the plurality of crystalline layers are substantially aligned with the concentric cylindrical layers. 5. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the oxide semiconductor comprises InGaZnO. 6. The three-dimensional (3D) non-volatile storage device of claim 1 , further comprising: a plurality of bit lines, each of the plurality of vertically-oriented NAND strings is associated with a bit line of the plurality of bit lines; and a plurality of metal bit line contacts, wherein each of the metal bit line contacts electrically connects one of the bit lines with a channel of one of the NAND strings, wherein the oxide semiconductor of the channel of a given NAND string is in direct electrical contact with its respective metal bit line contact. 7. The three-dimensional (3D) non-volatile storage device of claim 1 , further comprising: a metal source line that is associated with a group of the plurality of vertically-oriented NAND strings, wherein the oxide semiconductor of the channels of the group of NAND strings is in direct electrical contact with the metal source line. 8. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the plurality of non-volatile storage elements each comprise an information storage region that comprises a nitride charge trapping region. 9. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the crystalline structure of the oxide semiconductor is a single crystal substantially throughout the entire NAND channel. 10. The three-dimensional (3D) non-volatile storage device of claim 1 , wherein the oxide semiconductor comprises a plurality of crystal domains, substantially all of the crystal domains have a first axis that is aligned with respect to the cylindrical shape of the vertically-oriented channel. 11. A method of forming a 3D non-volatile storage device, the method comprising: providing a substrate; forming a plurality of insulator layers above the substrate; forming a plurality of conductive layers alternating with the insulator layers in a stack above the substrate; and forming a three-dimensional memory array comprising a plurality of vertically-oriented NAND strings extending through the conductive layers and insulator layers above the substrate, each vertically-oriented NAND string comprising a plurality of non-volatile storage elements and a vertically-oriented cylindrically shaped channel, comprising forming the vertically-oriented cylindrically shaped channel from an oxide semiconductor having a crystalline structure, the crystalline structure having an axis that is aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. 12. The method of claim 11 , wherein forming the three-dimensional memory array comprising the plurality of vertically-oriented NAND strings above the substrate comprises: forming vertical memory holes in a plurality of horizontal layers above the substrate, the memory holes having side walls; depositing material for the non-volatile storage elements on the side walls of the vertical memory holes leaving channel holes having side walls; and depositing a film of the oxide semiconductor on the side walls of the channel holes. 13. The method of claim 12 , wherein the material for the non-volatile storage elements on the side walls of the vertical memory holes comprises: a blocking layer, a charge trapping layer, and a tunneling layer. 14. The method of claim 13 , wherein the blocking layer comprises aluminum oxide and silicon oxide, the charge trapping layer comprises silicon nitride, and the tunneling layer comprises a stack of oxide, nitride, and oxide films. 15. The method of claim 11 , wherein each of the vertically-oriented NAND strings comprises a drain end, wherein forming the three-dimensional memory array comprising the plurality of vertically-oriented NAND strings above the substrate comprises: forming a metal bit line contact in direct electrical contact with the oxide semiconductor at the drain end of the vertically-oriented NAND strings. 16. The method of claim 11 , wherein forming the three-dimensional memory array comprising the plurality of vertically-oriented NAND strings above the substrate comprises: forming a metal source line that is associated with a group of the plurality of the vertically-oriented NAND strings, the plurality of the vertically-oriented NAND strings each having a source end; and forming the oxide semiconductor at the source end of group of vertically-oriented NAND strings in direct electrical contact with the metal source line. 17. The method of claim 11 , wherein forming the vertically-oriented cylindrically shaped channel from an oxide semiconductor having a crystalline structure having an axis (a, b, or c) that is aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel comprises: forming the crystalline structure of the oxide semiconductor as a substantially cylindrical shape having a cylindrical surface that is adjacent to the plurality of non-volatile storage elements, the crystalline structure having a radial axis that is perpendicular to the cylindrical surface, including forming the crystalline structure having a first axis that is substantially parallel to the radial axis substantially throughout the vertically-oriented channel. 18. The method of claim 11 , wherein forming the vertically-oriented cylindrically shaped channel from an
being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title
using physical deposition, e.g. vacuum deposition or sputtering · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.