Semiconductor devices compatible with mono-rank and multi-ranks

Patent metadata

Field	Value
Publication number	US-9209160-B2
Application number	US-201213535537-A
Country	US
Kind code	B2
Filing date	Jun 28, 2012
Priority date	Jul 20, 2011
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

A provided memory device is compatible with a mono-rank or multi-ranks. A plurality of memory layers are stacked in the memory device. The memory device receives an address signal and chip select signals in response to a chip identification signal and a mode signal used to determine a mono-rank or multi-ranks. The plurality of memory layers operate as the mono-rank accessed by the address signal, or operate as the multi-ranks accessed by the chip select signals.

First claim

What is claimed is:

1. A memory device comprising:
a first memory layer; and
a second memory layer stacked on the first memory layer,
wherein the first memory layer and second memory layer are configured to receive at least one address signal and/or at least one chip select signal, and
wherein the first memory layer and the second memory layer are configured to selectively operate in either a mono-rank mode or in a dual-rank mode responsive to the at least one address signal and/or the at least one chip select signal,
wherein the first memory layer and second memory layer are configured to receive the at least one address signal and/or the at least one chip select signal in response to a chip identification signal and a mode signal, and
wherein the mode signal is provided from a fuse box comprising a plurality of fuses in the first memory layer.

2. The memory device according to claim 1 ,
wherein the first memory layer and the second memory layer are a same type of memory chips,
wherein each of the first memory layer and the second memory layer comprises:
a core circuit unit in which a memory cell is formed; and
a peripheral circuit unit formed with respect to the memory cell.

3. The memory device according to claim 1 ,
wherein the first memory layer and the second memory layer are different types of memory chips,
wherein each of the first memory layer and the second memory layer comprises:
a core circuit unit in which a memory cell is formed; and
a peripheral circuit unit formed with respect to the memory cell,

wherein the first memory layer further comprises a master circuit region that is configured to interface with at least one device that is external to the memory device.

4. The memory device according to claim 1 ,
wherein each of the first memory layer and the second memory layer comprises:
a buffer unit that is configured to receive the at least one address signal and/or the at least one chip select signal in response to a chip identification signal; and
a chip select address control unit that is configured to determine whether the respective one of the first memory layer and/or the second memory layer is selected according to the at least one address signal and/or the at least one chip select signal in response to the chip identification signal and a mode signal, and to generate at least one chip select address control signal used to determine the mono-rank mode or the dual-rank mode.

5. A memory device comprising:
a first memory layer; and
a second memory layer stacked on the first memory layer,
wherein the first memory layer and second memory layer are configured to receive at least one address signal and/or at least one chip select signal, and
wherein the first memory layer and the second memory layer are configured to selectively operate in either a mono-rank mode or in a dual-rank mode responsive to the at least one address signal and/or the at least one chip select signal,
wherein each of the first memory layer and the second memory layer comprises:
a buffer unit that is configured to receive the at least one address signal and/or the at least one chip select signal in response to a chip identification signal; and
a chip select address control unit that is configured to determine whether the respective one of the first memory layer and/or the second memory layer is selected according to the at least one address signal and/or the at least one chip select signal in response to the chip identification signal and a mode signal, and to generate at least one chip select address control signal used to determine the mono-rank mode or the dual-rank mode,

wherein the at least one chip select signal comprises a first chip select signal and a second chip select signal, and
wherein output signal lines of the buffer unit of the first memory layer that receive the at least one address signal, the first chip select signal, and the second chip select signal are electrically connected to signal lines of the at least one address signal, the first chip select signal, and the second chip select signal that are provided to the chip select address control unit of the second memory layer using through silicon vias (TSVs).

6. A memory device comprising:
a first memory layer; and
a second memory layer stacked on the first memory layer,
wherein the first memory layer and second memory layer are configured to receive at least one address signal and/or at least one chip select signal, and
wherein the first memory layer and the second memory layer are configured to selectively operate in either a mono-rank mode or in a dual-rank mode responsive to the at least one address signal and/or the at least one chip select signal,
wherein each of the first memory layer and the second memory layer comprises:
a buffer unit that is configured to receive the at least one address signal and/or the at least one chip select signal in response to a chip identification signal; and
a chip select address control unit that is configured to determine whether the respective one of the first memory layer and/or the second memory layer is selected according to the at least one address signal and/or the at least one chip select signal in response to the chip identification signal and a mode signal, and to generate at least one chip select address control signal used to determine the mono-rank mode or the dual-rank mode wherein the chip select address control unit comprises:

a first logic unit that is configured to generate a first ME chip select address signal according to the first chip select signal, the at least one address signal, and the chip identification signal;
a first buffer that is configured to transfer the first ME chip select address signal to a first node in response to a complementary signal of the mode signal;
a second buffer that is configured to input a signal of the first node and to generate a ME chip select row address control signal;
a second logic unit that is configured to generate a first OTHER chip select address signal according to the first chip select signal, the address signal, and the chip identification signal;
a third buffer that is configured to transfer the first OTHER chip select address signal to a second node in response to the complementary signal of the mode signal;
a fourth buffer that is configured to input a signal of the second node and to generate another chip select row address control signal;
a third logic unit that is configured to generate a second ME chip select address signal according to the first chip select signal, the second chip select signal, and the chip identification signal;
a fifth buffer that is configured to transfer the second ME chip select address signal to the first node in response to the mode signal;
a fourth logic unit that is configured to generate a second OTHER chip select address signal according to the first chip select signal, the second chip select signal, and the chip identification signal; and
a sixth buffer that is configured to transfer the second OTHER chip select address signal to the second node in response to the mode signal.

7. The memory device according to claim 6 , wherein the chip select address control unit further comprises:
a seventh buffer that is enabled when power is applied to the memory device and that is configured to transfer the second ME chip select address signal;
an eighth buffer that is configured to generate an output of the seventh buffer as a ME chip select column address control signal;
a ninth buffer that is enabled when power is applied to the memory device and that is configured to transfer the second OTHER chip select address signal; and
a tenth buffer that is configured to generate an output of the ninth buffer as another chip select co

Assignees

• Lee Hoon
• Samsung Electronics Co Ltd

Inventors

• Lee Hoon

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title