Semiconductor device structure and method for forming the semiconductor device structure

Patent metadata

Field	Value
Publication number	US-12464789-B2
Application number	US-202217691335-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Mar 10, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

First claim

What is claimed is:

1 . A method for forming a semiconductor device structure, comprising:
forming first nanostructures and second nanostructures over a substrate; forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures; etching back the first metal gate layer over the first nanostructures and the second nanostructures; removing the first metal gate layer over the second nanostructures; and forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

2 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
etching back the second metal gate layer, wherein the first metal gate layer is covered by the second metal gate layer after etching back the second metal gate layer.

3 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a second glue layer over the second metal gate layer, wherein a top portion of the second glue layer is removed when etching back the second metal gate layer.

4 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a first glue layer surrounding the first metal gate layer and over the first metal gate layer; and etching back the first glue layer when etching back the first metal gate layer.

5 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a filling structure between the second nanostructures before forming the first metal gate layer; and removing the filling structure when removing the first metal gate layer over the second nanostructures.

6 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
oxidizing the first nanostructures and the second nanostructures after removing the first metal gate layer over the second nanostructures.

7 . A method for forming a semiconductor device structure, comprising:
forming a fin structure with alternating stacked first semiconductor layers and second semiconductor layers over a substrate; removing the first semiconductor layers to form a gate opening between the second semiconductor layers; depositing a first metal gate layer in the gate opening surrounding the second semiconductor layers; removing a top portion of the first metal gate layer; removing the first metal gate layer in a second region of the substrate; and depositing a second metal gate layer in the gate opening surrounding the second semiconductor layers in the second region of the substrate and over the first metal gate layer in a first region of the substrate, wherein a first bottommost surface of the second metal gate layer in the first region of the substrate is higher than a second bottommost surface of the second metal gate layer in the second region of the substrate.

8 . The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming a dummy gate structure across the fin structure; forming first spacer layers over opposite sides of the dummy gate structure; forming second spacer layers over opposite sides of the first spacer layers; and removing top portions of the first spacer layers before depositing the first metal gate layer.

9 . The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
depositing a coating layer over the first metal gate layer; and etching back the coating layer before removing the top portion of the first metal gate layer, wherein a top surface of the coating layer is substantially level with a top surface of the first metal gate layer after removing the top portion of the first metal gate layer.

10 . The method for forming the semiconductor device structure as claimed in claim 9 , further comprising:
removing the coating layer in the second region; and removing the first metal gate layer in the second region.

11 . The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming a second glue layer over the second metal gate layer; planarizing the second glue layer and the second metal gate layer; and etching back the second glue layer and the second metal gate layer over the fin structure.

12 . The method for forming the semiconductor device structure as claimed in claim 11 , wherein a seam is formed in the second glue layer.

13 . A method for forming a semiconductor device structure, comprising:
forming first nanostructures and second nanostructures over a substrate; forming a first metal gate layer surrounding the first nanostructures; forming a second metal gate layer surrounding the second nanostructures and over the first metal gate layer, wherein the second metal gate layer is in contact with a top surface of the first metal gate layer, wherein the first metal gate layer comprises N-work-function metal, and the second metal gate layer comprises P-work-function metal.

14 . The method for forming the semiconductor device structure as claimed in claim 13 , further comprising:
forming first spacer layers over opposite sides of the first metal gate layer over the first nanostructures; forming second spacer layers over opposite sides of the first spacer layers, wherein the top surface of the first metal gate layer is lower than top surfaces of the first spacer layers.

15 . The method for forming the semiconductor device structure as claimed in claim 14 , further comprising:
forming a cap layer formed over the second metal gate layer between the second spacer layers.

16 . The method for forming the semiconductor device structure as claimed in claim 13 , wherein the first metal gate layer is narrower than the second metal gate layer over the first nanostructures.

17 . The method for forming the semiconductor device structure as claimed in claim 13 , further comprising:
forming a first glue layer surrounding the first metal gate layer, wherein a top surface of the first glue layer is substantially level with the top surface of the first metal gate layer.

18 . The method for forming the semiconductor device structure as claimed in claim 7 , wherein the profile of the second metal gate layer in the first region of the substrate is different from the profile of the second metal gate layer in the second region of the substrate.

19 . The method for forming the semiconductor device structure as claimed in claim 7 , wherein a portion of the second metal gate layer in the first region of the substrate extends between opposite sidewalls of the first metal gate layer.

20 . The method for forming the semiconductor device structure as claimed in claim 13 , wherein a portion of the second metal gate layer extends between opposite sidewalls of the first metal gate layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Wen-Yao
• Chen Chia-Wei
• Hsu Wei-Cheng
• Hung Jo-Chun
• Chan Yung-Hsiang
• Chen Hui-Chi
• Lin Yen-Ta
• Yeh Te-Fu
• Wu Yun-Chen
• Chen Yen-Ju
• Sun Chih-Ming

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title