Semiconductor device with epitaxial bridge feature and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12464769-B2
Application number	US-202217883234-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	Feb 27, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

First claim

What is claimed is:

1 . A method, comprising:
forming a fin-shaped structure over a substrate and extending lengthwise along a direction, the fin-shaped structure comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers; forming an isolation structure over the substrate to surround a lower portion of the fin-shaped structure; forming a first dummy gate structure over a first channel region of the fin-shaped structure and a second dummy gate structure over a second channel region of the fin- shaped structure; etching a source/drain region of the fin-shaped structure to form a source/drain trench and to expose sidewalls of the plurality of first semiconductor layers and the plurality of second semiconductor layers, the source/drain region being disposed between the first channel region and the second channel region; recessing the source/drain trench such that sidewalls of the isolation structure are exposed in the source/drain trench; after the recessing, depositing a bottom feature over a bottom surface of the source/drain trench; after the depositing of the bottom feature, epitaxially growing a plurality of source/drain features extending between the plurality of first semiconductor layers under the first dummy gate structure and the plurality of first semiconductor layers under the second dummy gate structure; and forming a source/drain contact to wrap around each of the plurality of source/drain features and to interface the bottom feature, wherein each of the plurality of source/drain features comprises two edge portions and a middle portion disposed between the two edge portions along the direction, wherein a thickness of the middle portion is smaller than a thickness of the two edge portions.

2 . The method of claim 1 , wherein the plurality of first semiconductor layers comprise silicon and the plurality of second semiconductor layers comprise silicon germanium.

3 . The method of claim 1 , wherein the depositing of the bottom feature comprising epitaxially depositing the bottom feature using vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure CVD (LPCVD), and/or plasma-enhanced CVD (PECVD)), molecular beam epitaxy (MBE), or selective epitaxial growth (SEG).

4 . The method of claim 3 , wherein the bottom feature comprises undoped silicon carbide or undoped gallium arsenide.

5 . The method of claim 1 , further comprising:
after the epitaxially growing, depositing an interlayer dielectric (ILD) layer to wrap around each of the plurality of source/drain features; removing the first dummy gate structure and the second dummy gate structure; selectively removing the plurality of second semiconductor layers in the first channel region and the second channel region to suspend the plurality of first semiconductor layers in the first channel region and the second channel region; and after the selectively removing, forming a first gate structure to wrap around each of the plurality of first semiconductor layers in the first channel region and a second gate structure to wrap around each of the plurality of first semiconductor layers in the second channel region.

6 . The method of claim 1 , further comprising:
after the etching the source/drain region of the fin-shaped structure, partially and selectively recessing the sidewalls of the plurality of second semiconductor layers in the first channel region and the second channel region to form inner spacer recesses; and forming inner spacers in the inner spacer recesses.

7 . A method, comprising:
receiving a semiconductor structure comprising:
a substrate,
a fin-shaped structure disposed over the substrate and comprising:
a lower portion patterned from the substrate, and
a top portion including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers,

an isolation feature surrounding the lower portion of the fin-shaped structure;
a first dummy gate structure over a first channel region of the fin-shaped structure, and
a second dummy gate structure over a second channel region of the fin-shaped structure;
etching a source/drain region of the fin-shaped structure to form a source/drain trench and to expose sidewalls of the plurality of first semiconductor layers and the plurality of second semiconductor layers, the source/drain region being disposed between the first channel region and the second channel region; after the etching the source/drain region of the fin-shaped structure, partially and selectively recessing the sidewalls of the plurality of second semiconductor layers in the first channel region and the second channel region to form inner spacer recesses; forming inner spacers in the inner spacer recesses; after the forming of the inner spacers, further recessing the source/drain trench such that the source/drain trench partially extends into the lower portion; depositing a bottom feature over a bottom surface of the source/drain trench such that a bottom surface of the bottom feature is lower than a top surface of the lower portion in the first channel region; epitaxially growing a plurality of source/drain features extending between the plurality of first semiconductor layers under the first dummy gate structure and the plurality of first semiconductor layers under the second dummy gate structure; after the epitaxially growing, depositing an interlayer dielectric (ILD) layer to wrap around each of the plurality of source/drain features; and forming a source/drain contact to wrap around each of the plurality of source/drain features such that the source/drain contact is spaced apart from the inner spacers by the ILD layer.

8 . The method of claim 7 , wherein the bottom feature comprises undoped silicon carbide or undoped gallium arsenide.

9 . The method of claim 7 , further comprising:
removing the first dummy gate structure and the second dummy gate structure; selectively removing the plurality of second semiconductor layers in the first channel region and the second channel region to suspend the plurality of first semiconductor layers in the first channel region and the second channel region; and after the selectively removing, forming a first gate structure to wrap around each of the plurality of first semiconductor layers in the first channel region and a second gate structure to wrap around each of the plurality of first semiconductor layers in the second channel region.

10 . The method of claim 7 , wherein the source/drain contact comprises aluminum, tungsten, or copper.

11 . The method of claim 7 , further comprising:
before the forming of the source/drain contact, forming a metal silicide layer to wrap around each of the plurality of source/drain features.

12 . A method of forming a semiconductor device, comprising:
alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming dummy gate structures over the first and second semiconductor layers; forming source/drain (S/D) trenches along sidewalls of the dummy gate structures such that the first semiconductor layers and the second semiconductor layers are truncated by the S/D trenches; selectively removing edge portions of the second semiconductor layers; forming inner spacers to fill in the removed edge portions of the second semiconductor layers; after the forming of the inner spacers, further recessing the S/D

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ting-Yeh
• Lee Wei-Yang
• Lin Chia-Pin

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title