Method for bonding of chips

US12456720B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12456720-B2
Application numberUS-202418425205-A
CountryUS
Kind codeB2
Filing dateJan 29, 2024
Priority dateMar 2, 2017
Publication dateOct 28, 2025
Grant dateOct 28, 2025

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

First claim

Opening claim text (preview).

What is claimed is: 1. A method operatively associated with a bond head of a bonding device for bonding chips onto at least one of a semiconductor substrate or onto further chips, the method comprising: forming a liquid film on mounting points on the at least one of the semiconductor substrate or the further chips, the at least one of the semiconductor substrate or the further chips comprising a dielectric surface region and an electric surface region; positioning hybrid bond surfaces of the chips at the mounting points on the at least one of the semiconductor substrate or the further chips, by the bond head of a bonding device, the hybrid bond surfaces comprising a dielectric surface region and an electric surface region; using the bond head to directly bond the chips to the mounting points on the at least one of the semiconductor substrate or the further chips, wherein using the bond head to directly bond the chips comprises first bonding a center of the chips onto the liquid film and then bonding outwards from the center of the chips onto the liquid film while holding the chips by the bond head; and releasing the chips from fixation by the bond head, wherein the electric surface region of the chips and the electric surface region of the at least one of the semiconductor substrate or the further chips self-align congruently with one another. 2. The method according to claim 1 , comprising prior to positioning the hybrid bond surfaces, fixing a substrate onto a carrier and subsequently separating the substrate into the chips. 3. The method according to claim 2 , comprising prior to fixing the substrate on the carrier, cleaning a bond surface of the substrate. 4. The method according to claim 3 , wherein cleaning comprises cleaning the bond surfaces of the chips as the chips are removed from the carrier and/or while transporting the chips to bond positions. 5. The method according to claim 3 , wherein separating comprises mechanically separating the chips at joints having previously been introduced into the bond surface of the substrate. 6. The method according to claim 2 , wherein cleaning comprises cleaning the bond surfaces of the chips as the chips are removed from the carrier and/or while transporting the chips to bond positions. 7. The method according to claim 6 , wherein separating comprises mechanically separating the chips at joints having previously been introduced into the bond surface of the substrate. 8. The method according to claim 2 , wherein separating comprises mechanically separating the chips at joints having previously been introduced into the bond surface of the substrate.

Assignees

Inventors

Classifications

  • Direct bonding of chips, wafers or substrates · CPC title

  • batch processes · CPC title

  • Means for applying energy, e.g. ovens or lasers · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

  • for alignment · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12456720B2 cover?
A method for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.
Who is the assignee on this patent?
Ev Group E Thallner Gmbh
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).