Semiconductor device
US-10217752-B2 · Feb 26, 2019 · US
Semiconductor device
US12453073B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12453073-B2 |
| Application number | US-202017616441-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 25, 2020 |
| Priority date | Jun 7, 2019 |
| Publication date | Oct 21, 2025 |
| Grant date | Oct 21, 2025 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a first layer, a second layer, and a third layer over a substrate, wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si, wherein a second transistor included in the second layer comprises a second semiconductor layer comprising Ga, wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn, wherein the first semiconductor layer of the first transistor is formed using the substrate, wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate, and wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer. 2. The semiconductor device according to claim 1 , wherein the third transistor comprises a region overlapping with the first transistor. 3. The semiconductor device according to claim 1 , wherein the third transistor comprises a region overlapping with the second transistor. 4. The semiconductor device according to claim 1 , further comprising a fourth layer, wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and wherein the fourth transistor comprises a region overlapping with the third transistor. 5. The semiconductor device according to claim 1 , wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed. 6. A semiconductor device comprising: a first layer, a second layer, and a third layer over a substrate, wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si, wherein a second transistor included in the second layer comprises a second semiconductor layer comprising Ga, wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn, wherein the first semiconductor layer of the first transistor is formed using the substrate, wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate, wherein the second transistor has a recessed gate structure, and wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer. 7. The semiconductor device according to claim 6 , wherein the third transistor comprises a region overlapping with the first transistor. 8. The semiconductor device according to claim 6 , wherein the third transistor comprises a region overlapping with the second transistor. 9. The semiconductor device according to claim 6 , further comprising a fourth layer, wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and wherein the fourth transistor comprises a region overlapping with the third transistor. 10. The semiconductor device according to claim 6 , wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed. 11. A semiconductor device comprising: a first layer, a second layer, and a third layer over a substrate, wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si, wherein a second transistor included in the second layer comprises a second semiconductor layer comprising oxygen, wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn, wherein the first semiconductor layer of the first transistor is formed using the substrate, wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate, wherein the second transistor does not overlap with the first transistor, and wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer. 12. The semiconductor device according to claim 11 , wherein the third transistor comprises a region overlapping with the first transistor. 13. The semiconductor device according to claim 11 , wherein the third transistor comprises a region overlapping with the second transistor. 14. The semiconductor device according to claim 11 , further comprising a fourth layer, wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and wherein the fourth transistor comprises a region overlapping with the third transistor. 15. The semiconductor device according to claim 11 , wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed.
Assignees
Inventors
Classifications
Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title
integrated with passive devices, e.g. auxiliary capacitors · CPC title
Interconnections, e.g. scanning lines · CPC title
comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title
wherein the TFTs are in active matrices · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12453073B2 cover?
- A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third …
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).