CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof

Patent metadata

Field	Value
Publication number	US-9070758-B2
Application number	US-201213525644-A
Country	US
Kind code	B2
Filing date	Jun 18, 2012
Priority date	Jun 20, 2011
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.

First claim

What is claimed is:

1. A CMOS compatible method for manufacturing a Group III-nitride HEMT having a gate electrode and Au-free source and drain ohmic contacts, comprising:
a) providing a substrate;
b) forming a stack of Group III-nitride layers on the substrate;
c) forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of Group III-nitride layers, wherein the first passivation layer is deposited at a temperature between 900° C. and 1250° C. by a first chemical vapor deposition technique, and wherein the first passivation layer is deposited in-situ with the stack of Group III-nitride layers;
d) forming a dielectric layer overlying and in contact with the first passivation layer, the dielectric layer comprising a high-k dielectric material;
e) forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer, wherein the second passivation layer is deposited at a temperature higher than 450° C. by a second chemical vapor deposition technique; and thereafter
f) forming source and drain ohmic contacts, and a gate electrode in such a way that a gate dielectric is formed comprising the first passivation layer and at least part of the dielectric layer, wherein forming source and drain ohmic contacts comprises patterning source and drain ohmic contact regions by selectively etching the second passivation layer, the dielectric layer, and the first passivation layer, and forming ohmic contacts by deposition of an Au-free metal layer, patterning the metal layer, and forming an ohmic alloy at a temperature between 500° C. and 850° C. and below a crystallization temperature of the high-k material of the gate dielectric, wherein forming the gate electrode comprises patterning a gate trench by selective etching of the second passivation layer towards the dielectric layer and forming the gate electrode in the gate trench by deposition of a metal gate layer and patterning the metal gate layer such that the second passivation layer is thinner in an exposed region between an edge of the gate electrode and the source and drain contacts when compared to an original thickness as-deposited in regions covered by the gate electrode.

2. The method of claim 1 , wherein at least one of the first passivation layer and the second passivation layer comprises Si 3 N 4 .

3. The method of claim 1 , wherein the second chemical vapor deposition technique is selected from the group consisting of low pressure chemical vapor deposition and metal organic chemical vapor deposition.

4. The method of claim 1 , wherein patterning the metal layer comprises a dry-etch process of the metal layer wherein the dry-etch process of the metal layer consumes partially the second passivation layer.

5. The method of claim 1 , wherein patterning the metal gate layer comprises a dry-etch process of the metal gate layer wherein the dry-etch process of the metal gate layer consumes partially the second passivation layer.

6. The method of claim 1 , further comprising: forming a dielectric cap layer on whichever is formed first of the source and drain ohmic contacts or the gate electrode, thereby protecting the source and drain ohmic contacts or the gate electrode during a subsequent metal layer or metal gate layer deposition.

7. The method of claim 1 , wherein the dielectric layer comprises Al.

8. The method of claim 7 , wherein the dielectric layer comprises Al 2 O 3 .

9. The method of claim 1 , wherein the first passivation layer has a thickness of at least 0.5 nm.

10. The method of claim 1 , wherein the second passivation layer has a thickness of at least 50 nm.

11. The method of claim 1 , wherein the first passivation layer is deposited at a temperature of 1100° C.

Assignees

• Van Hove Marleen
• Imec

Inventors

• Van Hove Marleen

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43 Primary

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title