Semiconductor device

Patent metadata

Field	Value
Publication number	US-10217752-B2
Application number	US-201715591150-A
Country	US
Kind code	B2
Filing date	May 10, 2017
Priority date	Mar 7, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a memory cell comprising a first transistor, a second transistor, and a capacitor,
wherein:
a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,
the first transistor and the second transistor each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),
in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),
in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+f).

2. The semiconductor device according to claim 1 , wherein the element M is aluminum, gallium, yttrium, or tin.

3. The semiconductor device according to claim 1 , wherein the first transistor is over the second transistor.

4. The semiconductor device according to claim 1 , wherein in a height direction, the capacitor is between the first transistor and the second transistor.

5. The semiconductor device according to claim 1 , wherein:
the second transistor has a higher mobility than the first transistor, and
the first transistor has a lower off-state current than the second transistor.

6. A semiconductor device comprising:
a first memory cell comprising a first transistor, a second transistor, and a capacitor; and
a second memory cell comprising a first transistor, a second transistor, and a capacitor,
wherein in each of the first and second memory cells:
a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,
the first and second transistors each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),
in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),
in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+f).

7. The semiconductor device according to claim 6 , wherein the second memory cell is over the first memory cell.

8. The semiconductor device according to claim 6 , wherein the element M is aluminum, gallium, yttrium, or tin.

9. The semiconductor device according to claim 6 ,
wherein the first transistor is over the second transistor in each of the first and second memory cells.

10. The semiconductor device according to claim 6 , wherein in a height direction the capacitor is between the first transistor and the second transistor in each of the first and second memory cells.

11. The semiconductor device according to claim 6 , wherein in each of the first and second memory cells:
the second transistor has a higher mobility than the first transistor, and
the first transistor has a lower off-slate current than the second transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Atsumi Tomoaki
• Nagatsuka Shuhei
• Moriwaka Tamae
• Endo Yuta

Classifications

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title