Semiconductor device

Patent metadata

Field	Value
Publication number	US-9653611-B2
Application number	US-201514637542-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Mar 7, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells each comprising a first transistor, a second transistor, and a capacitor,
wherein:
the first transistor overlaps with the second transistor with the capacitor interposed therebetween,
a first semiconductor layer in the first transistor and a second semiconductor layer in the second transistor include an oxide semiconductor,
a first terminal of the capacitor is electrically connected to one of source and drain electrodes of the first transistor and a gate electrode of the second transistor, and
jth (j is a natural number of 2 to c) sub memory cell is arranged over j−1th sub memory cell.

2. A semiconductor device comprising:
a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells each comprising a first transistor, a second transistor, and a capacitor,
wherein:
the first transistor overlaps with the second transistor with the capacitor interposed therebetween,
a first semiconductor layer in the first transistor and a second semiconductor layer in the second transistor include an oxide semiconductor,
a first terminal of the capacitor is electrically connected to one of source and drain electrodes of the first transistor and a gate electrode of the second transistor,
the second semiconductor layer in jth (j is a natural number of 2 to c) sub memory cell and the first semiconductor layer in j−1th sub memory cell are in contact with an upper surface of a first insulating film, and
the gate electrode of the second transistor in the jth sub memory cell and the gate electrode of the first transistor in the j−1th sub memory cell are in contact with a lower surface of a second insulating film.

3. A semiconductor device comprising:
a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells each comprising a first transistor, a second transistor, and a capacitor,
wherein:
jth (j is a natural number of 2 to c) sub memory cell is arranged over j−1th sub memory cell,
the first transistor is positioned over the second transistor with the capacitor therebetween,
a first semiconductor layer in the first transistor and a second semiconductor layer in the second transistor include an oxide semiconductor,
a first terminal of the capacitor is electrically connected to one of source and drain electrodes of the first transistor and a gate electrode of the second transistor,
one of the first semiconductor layer and the second semiconductor layer in the first sub memory cell, and a third semiconductor layer in a third transistor adjacent to the first sub memory cell are over and in contact with a first insulating film, and
one of the first semiconductor layer and the second semiconductor layer in the cth sub memory cell, and a fourth semiconductor layer in a fourth transistor adjacent to the cth sub memory cell are over and in contact with a second insulating film.

4. The semiconductor device according to claim 1 ,
wherein:
the oxide semiconductor includes In, an element represented by M, and Zn,
the atomic ratio of In to M and Zn of the oxide semiconductor included in the first semiconductor layer satisfies In:M:Zn=g:h:i (each of g, h, i is a positive number),
the atomic ratio of In to M and Zn of the oxide semiconductor included in the second semiconductor layer satisfies In:M:Zn=d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+j).

5. The semiconductor device according to claim 2 ,
wherein:
the oxide semiconductor includes In, an element represented by M, and Zn,
the atomic ratio of In to M and Zn of the oxide semiconductor included in the first semiconductor layer satisfies In:M:Zn=g:h:i (each of g, h, i is a positive number),
the atomic ratio of In to M and Zn of the oxide semiconductor included in the second semiconductor layer satisfies In:M:Zn=d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+j).

6. The semiconductor device according to claim 3 ,
wherein:
the oxide semiconductor includes In, an element represented by M, and Zn,
the atomic ratio of In to M and Zn of the oxide semiconductor included in the first semiconductor layer satisfies In:M:Zn=g:h:i (each of g, h, i is a positive number),
the atomic ratio of In to M and Zn of the oxide semiconductor included in the second semiconductor layer satisfies In:M:Zn=d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+j).

7. The semiconductor device according to claim 4 , wherein the element represented by M is one of aluminum, gallium, yttrium, and tin.

8. The semiconductor device according to claim 5 , wherein the element represented by M is one of aluminum, gallium, yttrium, and tin.

9. The semiconductor device according to claim 6 , wherein the element represented by M is one of aluminum, gallium, yttrium, and tin.

10. The semiconductor device according to claim 1 , further comprising:
a first wiring and a second wiring,
wherein the first wiring is configured to electrically connect to the first terminal of the capacitor and the one of source and drain electrodes of the first transistor, and
wherein the second is configured to electrically connect to the first terminal of the capacitor and the gate electrode of the second transistor.

11. The semiconductor device according to claim 2 , further comprising:
a first wiring and a second wiring,
wherein the first wiring is configured to electrically connect to the first terminal of the capacitor and the one of source and drain electrodes of the first transistor, and
wherein the second is configured to electrically connect to the first terminal of the capacitor and the gate electrode of the second transistor.

12. The semiconductor device according to claim 3 , further comprising:
a first wiring and a second wiring,
wherein the first wiring is configured to electrically connect to the first terminal of the capacitor and the one of source and drain electrodes of the first transistor, and
wherein the second is configured to electrically connect to the first terminal of the capacitor and the gate electrode of the second transistor.

13. The semiconductor device according to claim 10 , wherein the first wiring and the second wiring overlap with each other.

14. The semiconductor device according to claim 11 , wherein the first wiring and the second wiring overlap with each other.

15. The semiconductor device according to claim 12 , wherein the first wiring and the second wiring overlap with each other.

16. The semiconductor device according to claim 1 ,
wherein a mobility of the second transistor is higher than that of the first transistor, and
wherein an off-state current of the first transistor is lower than that of the second transistor.

17. The semiconductor device according to claim 2 ,
wherein a mobility of the second transistor is higher than that of the first transistor, and
wherein an off-state current of the first transistor is lower than that of the second transistor.

18. The semiconductor device according to claim 3 ,
wherein a mobility of the second transistor is higher than that of the first transistor, and
wherein an off-state current of the first transistor is lower than that of the second transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Atsumi Tomoaki
• Nagatsuka Shuhei
• Moriwaka Tamae
• Endo Yuta

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title