Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9660085-B2
Application number	US-201315036780-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

First claim

What is claimed is:

1. A semiconductor transistor structure, comprising:
a silicon substrate;
an insulating layer formed on top of the silicon substrate;
a trench extending through the insulating layer and into the silicon substrate, the trench containing a trench material comprising a first III-V semiconductor material;
a channel structure formed directly on top of the insulating layer and adjacent to the trench, the channel structure formed with a channel material comprising a second III-V semiconductor material having a defect density lower than a defect density of the trench material;
a source and drain formed on opposite sides of the channel structure, the source formed on top of the trench material; and

a gate electrode formed above the channel structure.

2. The semiconductor transistor structure of claim 1 , wherein the trench material and the channel material comprise gallium nitride.

3. The semiconductor transistor structure of claim 1 , wherein the channel material has a defect density less than 1E9 cm-2.

4. The semiconductor transistor structure of claim 1 , wherein the trench material has a defect density greater than 1E9 cm-2.

5. The semiconductor transistor structure of claim 1 , wherein the source is formed on top of the trench material and the drain is formed on top of the insulating layer.

6. The semiconductor transistor structure of claim 5 , wherein the source is thermally coupled with the silicon substrate.

7. The semiconductor transistor structure of claim 1 , wherein the source and drain comprise indium gallium nitride.

8. The semiconductor transistor structure of claim 7 , wherein the indium gallium nitride has an N+ doping concentration higher than 5E19 cm-3.

9. The semiconductor transistor structure of claim 1 , wherein the trench material and channel structure comprise GaN, and the source and drain comprise InGaN.

10. A system-on-chip, comprising:
a semiconductor substrate;
a metal oxide semiconductor transistor formed on the semiconductor substrate; and
a wide band gap semiconductor transistor formed on the semiconductor substrate and adjacent to the metal oxide semiconductor transistor, comprising:
an insulating layer formed on top of the semiconductor substrate;
a trench formed through the insulating layer and extending into the semiconductor substrate, the trench filled with a trench material comprising a III-V semiconductor material;
a channel structure formed directly on top of the insulating layer and adjacent to the trench, the channel structure formed with a channel material comprising a III-V semiconductor material having a defect density lower than a defect density of the trench material;
a source and drain formed on opposite sides of the channel structure; and

a gate electrode formed on top of the channel structure.

11. The semiconductor transistor structure of claim 10 , wherein the trench material and the channel material comprise gallium nitride.

12. The semiconductor transistor structure of claim 10 , wherein the channel material has a defect density of less than 1E9 cm-2.

13. The semiconductor transistor structure of claim 10 , wherein the trench material has a defect density greater than 1E9 cm-2.

14. The semiconductor transistor structure of claim 10 , wherein the source is formed on top of the trench material and the drain is formed on top of the insulating layer.

15. The semiconductor transistor structure of claim 10 , wherein the source is thermally coupled with the semiconductor substrate.

16. The semiconductor transistor structure of claim 10 , wherein the source and drain comprise indium gallium nitride.

Assignees

• Intel Corp
• Intel Corp

Inventors

• Then Han Wui
• Chau Robert S
• Dasgupta Sansaptak
• Radosavljevic Marko
• Chu-Kung Benjamin
• Sung Seung Hoon Hoon
• Gardner Sanaz K
• Pillarisetty Ravi

Classifications

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D84/01

  Manufacture or treatment · CPC title