Wide band gap transistor on non-native semiconductor substrate

Patent metadata

Field	Value
Publication number	US-10032911-B2
Application number	US-201715499794-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Dec 23, 2013
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
an insulating layer above a substrate, the insulating layer having a top surface;
a first III-V semiconductor material above the substrate and laterally adjacent to the insulating layer, wherein the first III-V semiconductor material has a top surface substantially co- planar with the top surface of the insulating layer;
a channel structure on the top surface of insulating layer, the channel structure having a channel material comprising a second III-V semiconductor material, the channel structure having a first side opposite a second side;
a first source/drain structure on the first side of the channel structure, the first source/drain channel structure having a bottom surface on the insulating layer;
a second source/drain structure on the second side of the channel structure, the second source/drain structure having a bottom surface on the top surface of the first III-V semiconductor material, wherein the bottom surface of the second source/drain structure is substantially co-planar with the bottom surface of the first source/drain structure; and
a gate electrode above the channel structure.

2. The integrated circuit structure of claim 1 , wherein the first source/drain structure is a source of the integrated circuit structure, and the second is a drain of the integrated circuit structure.

3. The integrated circuit structure of claim 1 , wherein the first source/drain structure is a drain of the integrated circuit structure, and the second is a source of the integrated circuit structure.

4. The integrated circuit structure of claim 1 , wherein the first III-V semiconductor material and the channel material comprise gallium nitride.

5. The integrated circuit structure of claim 4 , wherein the first source/drain structure and the second source/drain structure comprise indium gallium nitride.

6. The integrated circuit structure of claim 1 , wherein the first source/drain structure and the second source/drain structure comprise indium gallium nitride.

7. The integrated circuit structure of claim 1 , wherein the second source/drain structure is thermally coupled with the substrate.

8. A semiconductor transistor structure, comprising: a silicon substrate;
an insulating layer formed on top of the silicon substrate;
a trench extending through the insulating layer and into the silicon substrate, the trench containing a trench material comprising a first III-V semiconductor material;
a channel structure formed directly on top of the insulating layer and adjacent to the trench, the channel structure formed with a channel material comprising a second III-V semiconductor material having a defect density lower than a defect density of the trench material;
a source and drain formed on opposite sides of the channel structure, the drain formed on top of the trench material; and
a gate electrode formed above the channel structure.

9. The semiconductor transistor structure of claim 8 , wherein the trench material and the channel material comprise gallium nitride.

10. The semiconductor transistor structure of claim 8 , wherein the channel material has a defect density less than 1E9 cm −2 .

11. The semiconductor transistor structure of claim 8 , wherein the trench material has a defect density greater than 1E9cm −2 .

12. The semiconductor transistor structure of claim 8 , wherein the drain is formed on top of the trench material and the source is formed on top of the insulating layer.

13. The semiconductor transistor structure of claim 12 , wherein the drain is thermally coupled with the silicon substrate.

14. The semiconductor transistor structure of claim 8 , wherein the source and drain comprise indium gallium nitride.

15. The semiconductor transistor structure of claim 14 , wherein the indium gallium nitride has an N + doping concentration higher than 5E19 cm −3 .

16. The semiconductor transistor structure of claim 8 , wherein the trench material and channel structure comprise GaN, and the source and drain comprise InGaN.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Chau Robert S
• Dasgupta Sansaptak
• Radosavljevic Marko
• Chu-Kung Benjamin
• Sung Seung Hoon
• Gardner Sanaz
• Pillarisetty Ravi

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3416

  Nitrides · CPC title