Memory device transmitting and receiving data at high speed and low power

Patent metadata

Field	Value
Publication number	US-12444457-B2
Application number	US-202318458743-A
Country	US
Kind code	B2
Filing date	Aug 30, 2023
Priority date	Jan 21, 2020
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

First claim

What is claimed is:

1. A memory device comprising:
a logic die configured to communicate with a host device through a plurality of channels, each of which including an independent interface; and
a plurality of memory dies stacked on the logic die, each of the plurality of memory dies including a memory cell array corresponding to at least one of the plurality of channels,
wherein the logic die includes:
first pins configured to receive a clock signal having a first clock frequency;
second pins configured to receive a write command/address signal based on the clock signal;
third pins configured to receive a write strobe signal having a second clock frequency; and
DQ pins configured to receive a write data signal based on a plurality of internal write data strobe signal, the plurality of internal write data strobe signal being based on write strobe signal,
wherein the first clock frequency is half of the second clock frequency,
wherein the write strobe signal includes a main toggling period aligned with the write data signal,
wherein a number of write pre-amble cycles of the write strobe signal before the main toggling period is even-numbered, and
wherein a number of write post-amble cycles of the write strobe signal after the main toggling period is even-numbered.

2. The memory device of claim 1 , wherein the number of write pre-amble cycles of the write strobe signal before the main toggling period is two, and
wherein the number of write post-amble cycles of the write strobe signal after the main toggling period is two.

3. The memory device of claim 1 , wherein each of the plurality of memory dies includes a plurality of memory banks.

4. The memory device of claim 1 , wherein the plurality of memory dies stacked on the logic die are electrically connected through silicon vias.

5. The memory device of claim 1 , wherein the logic die includes:
a write data strobe signal divider configured to generate the plurality of internal write data strobe signals that toggle based on toggling of the write strobe signal, the plurality of internal write data strobe signals toggling with different phases, respectively.

6. The memory device of claim 5 , wherein the logic die further includes:
a command/address receiver configured to receive the write command/address signal through the first pins;
a control logic circuit configured to generate an internal command based on the write command/address signal; and
a data transceiver configured to receive write data based on the plurality of internal write data strobe signals,
wherein a memory die from among the plurality of memory dies is configured to store the write data in response to the internal command.

7. The memory device of claim 5 , wherein the plurality of internal write data strobe signals include a first write data strobe signal, a second write data strobe signal, a third write data strobe signal, and a fourth write data strobe signal respectively corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, and
wherein a frequency of each of the first through fourth internal write data strobe signals is half of a frequency of the write data strobe signal.

8. A memory device comprising:
a logic die configured to communicate with a host device through a plurality of channels, each of which includes an independent interface; and
a plurality of memory dies stacked on the logic die, each of the plurality of memory dies including a memory cell array corresponding to at least one of the plurality of channels,
wherein the logic die includes:
first pins configured to receive a clock signal having a first clock frequency;
second pins configured to receive a write command/address signal based on the clock signal;
third pins configured to receive a write strobe signal having a second clock frequency;
fourth pins configured to transmit a read strobe signal having a third clock frequency, the read strobe signal being based on the write strobe signal; and
DQ pins configured to transmit a read data signal based on the read strobe signal,
wherein the first clock frequency is half of the second clock frequency and the third clock frequency,
wherein the write strobe signal includes a main toggling period,
wherein a number of read pre-amble cycles of the write strobe signal before the main toggling period is even-numbered, and
wherein a number of read post-amble cycles of the write strobe signal after the main toggling period is even-numbered.

9. The memory device of claim 8 , wherein the number of read pre-amble cycles of the write strobe signal before the main toggling period is four, and
wherein the number of read post-amble cycles of the write strobe signal after the main toggling period is two.

10. The memory device of claim 8 , wherein each of the plurality of memory dies includes a plurality of memory banks.

11. The memory device of claim 8 , wherein the plurality of memory dies stacked on the logic die are electrically connected through silicon vias.

12. The memory device of claim 8 , wherein the logic die includes:
a write data strobe signal divider configured to generate a plurality of internal write data strobe signals that toggle based on toggling of the write strobe signal, the plurality of internal write data strobe signals toggling with different phases, respectively.

13. The memory device of claim 12 , wherein the logic die further includes:
a command/address receiver configured to receive the write command/address signal through the first pins;
a control logic circuit configured to generate an internal command based on the write command/address signal; and
a data transceiver configured to receive write data based on the plurality of internal write data strobe signals,
wherein a memory die from among the plurality of memory dies is configured to store the write data in response to the internal command.

14. The memory device of claim 12 , wherein the plurality of internal write data strobe signals include a first write data strobe signal, a second write data strobe signal, a third write data strobe signal, and a fourth write data strobe signal respectively corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, and
wherein a frequency of each of the first through fourth internal write data strobe signals is half of a frequency of the write data strobe signal.

15. A memory device comprising:
a logic die configured to communicate with a host device through a plurality of channels, each of which includes an independent interface; and
a plurality of memory dies stacked on the logic die, each of the plurality of memory dies including a memory cell array corresponding to at least one of the plurality of channels,
wherein the logic die includes:
first pins configured to receive a clock signal having a first clock frequency;
second pins configured to receive a write command/address signal based on the clock signal;
third pins configured to receive a write strobe signal having a second clock frequency;
fourth pins configured to transmit a read strobe signal having a third clock frequency, the read strobe signal being based on the write strobe signal; and
DQ pins configured to transmit a read data signal based on the read strobe signal,
wherein the first clock frequency is half of the second clock frequency and the third clock frequency,
wherein the read strobe signal includes a main toggling period aligned with the read data signal,
wherein a number of read pre-amble cycles of the read strobe signal before the main toggling period is even-numbered, and
wherein a number of rea

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Byongmo
• Kim Jihye
• Ryu Je Min
• Kil Beomyong
• Ahn Sungoh

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title