Memory device transmitting and receiving data at high speed and low power

Patent metadata

Field	Value
Publication number	US-11769547-B2
Application number	US-202217685067-A
Country	US
Kind code	B2
Filing date	Mar 2, 2022
Priority date	Jan 21, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

First claim

What is claimed is:

1. A method for using a high bandwidth memory controller, the method comprising:
providing a clock signal having a first clock frequency;
providing a write strobe signal having a second clock frequency;
providing a write command/address signal based on the clock signal;
providing a write data signal based on the write strobe signal;
generating, by a phase locked loop, a first internal clock signal;
generating, by a phase controller, a second internal clock signal based on the first internal clock signal;
dividing, by an internal clock divider, the first internal clock signal to generate a first divided internal clock signal and a second divided internal clock signal;
generating, by a first transmitter, the write data signal including write data based on the second internal clock signal;
generating, by a second transmitter, the first internal clock signal as the write strobe signal;
generating, by a third transmitter, the first divided internal clock signal as the clock signal; and
generating, by a fourth transmitter, the write command/address signal based on the second divided internal clock signal,
wherein the first clock frequency is half of the second clock frequency, and
wherein the write strobe signal has two cycles of pre-amble before the write data signal and the write strobe signal has two cycles of post-amble after the write data signal.

2. The method of claim 1 , wherein the clock signal and the write strobe signal are generated from a same phase locked loop.

3. The method of claim 1 , wherein a sum of a number of pre-amble cycles of the write strobe signal and a number of post-amble cycles of the write strobe signal is even-numbered.

4. The method of claim 1 , wherein the write strobe signal maintains a static low value or a static high value before the write strobe signal starts to toggle.

5. The method of claim 1 , wherein the first internal clock signal and the second internal clock signal are 90 degrees out of phase.

6. The method of claim 1 , wherein an edge timing of the first divided internal clock signal is identical to an edge timing of the first internal clock signal.

7. The method of claim 1 , wherein the first divided internal clock signal the second divided internal clock signal are 270 degree out of phase.

8. A method for using a high bandwidth memory controller, the method comprising:
providing a clock signal having a first clock frequency;
providing a write strobe signal having a second clock frequency;
providing a read command/address signal based on the clock signal;
receiving a read data signal based on a read strobe signal generated from the write strobe signal; and
wherein the first clock frequency is half of the second clock frequency, and
wherein the read strobe signal has a plurality of pre-amble cycles before the read data signal and the read strobe signal has a plurality of post-amble cycles after the read data signal.

9. The method of claim 8 , wherein the clock signal and the read strobe signal are generated from a same phase locked loop.

10. The method of claim 8 , wherein a sum of a number of pre-amble cycles of the write strobe signal and a number of post-amble cycles of the write strobe signal is even-numbered.

11. The method of claim 8 , wherein the read strobe signal maintains a static low value or a static high value before the read strobe signal starts to toggle.

12. A memory controller comprising:
a phase locked loop configured to generate a first internal clock signal;
a phase controller configured to generate a second internal clock signal based on the first internal clock signal;
an internal clock divider configured to divide the first internal clock signal to generate a first divided internal clock signal and a second divided internal clock signal;
a first transmitter configured to transmit a write data signal including write data based on the second internal clock signal;
a second transmitter configured to transmit the first internal clock signal as a write strobe signal;
a third transmitter configured to transmit the first divided internal clock signal as a clock signal; and
a fourth transmitter configured to transmit the write command/address signal based on the second divided internal clock signal.

13. The memory controller of claim 12 , wherein the clock signal and the write strobe signal are generated from a same phase locked loop.

14. The memory controller of claim 12 , wherein a sum of a number of pre-amble cycles of the write strobe signal and a number of post-amble cycles of the write strobe signal is even-numbered.

15. The memory controller of claim 12 , wherein the write strobe signal maintains a static low value or a static high value before the write strobe signal starts to toggle.

16. The memory controller of claim 12 , wherein the first internal clock signal and the second internal clock signal are 90 degrees out of phase.

17. The memory controller of claim 12 , wherein an edge timing of the first divided internal clock signal is identical to an edge timing of the first internal clock signal.

18. The memory controller of claim 12 , wherein the first divided internal clock signal the second divided internal clock signal are 270 degree out of phase.

19. The memory controller of claim 18 , wherein a frequency of the first divided internal clock signal and the second divided internal clock signal is half a frequency of the second internal clock signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Byongmo
• Kim Jihye
• Ryu Je Min
• Kil Beomyong
• Ahn Sungoh

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title