Memory device transmitting and receiving data at high speed and low power

Patent metadata

Field	Value
Publication number	US-11295808-B2
Application number	US-202017084345-A
Country	US
Kind code	B2
Filing date	Oct 29, 2020
Priority date	Jan 21, 2020
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

First claim

What is claimed is:

1. A memory device comprising:
a buffer die configured to communicate with a host device through a plurality of channels; and
a plurality of core dies stacked on the buffer die and being connected to the buffer die through a silicon through electrode, each of the plurality of core dies including a memory cell array corresponding to at least one of the plurality of channels,
wherein the buffer die includes:
a command/address receiver configured to receive a command provided from the host device to a first channel of the plurality of channels, based on a clock signal provided from the host device to the first channel;
a control logic circuit configured to generate an internal command based on the command received from the command/address receiver and to generate a reset signal before a write data strobe signal provided from the host device to the first channel starts to toggle;
a write data strobe signal divider configured to generate a plurality of internal write data strobe signals that toggle based on toggling of the write data strobe signal, the plurality of internal write data strobe signals toggling with different phases, respectively, and to initialize the plurality of internal write data strobe signals to given values based on the reset signal; and
a data transceiver configured to receive write data provided from the host device to the first channel based on the plurality of internal write data strobe signals,
wherein a core die from among the plurality of core dies that supports the first channel is configured to store the write data transmitted from the buffer die based on the internal command transmitted from the buffer die.

2. The memory device of claim 1 , wherein the control logic circuit is configured to generate the reset signal based on the command received from the command/address receiver, or based on a power state of the memory device.

3. The memory device of claim 2 , wherein the control logic circuit is configured to generate the reset signal based on the power state of the memory device, and when the memory device is in a power-up state, the control logic circuit is configured to generate the reset signal.

4. The memory device of claim 2 , wherein the control logic circuit is configured to generate the reset signal based on the power state of the memory device, and when the first channel of the memory device is in a power down exit state or a self-refresh exit state, the control logic circuit is configured to generate the reset signal.

5. The memory device of claim 2 , wherein the control logic circuit is configured to generate the reset signal based on the command received from the command/address receiver, and
wherein the control logic circuit is configured to generate the reset signal based on at least one of an active command, a write command, a read command, and a divider reset command.

6. The memory device of claim 1 , wherein a sum of a number of pre-amble cycles of the write data strobe signal and a number of post-amble cycles of the write data strobe signal is even-numbered.

7. The memory device of claim 1 , wherein the write data strobe signal maintains a static low value or a static high value before the write data strobe signal starts to toggle.

8. The memory device of claim 1 , wherein the given values are defined based on a number of pre-amble cycles of the write data strobe signal.

9. The memory device of claim 1 , wherein, based on the reset signal, the write data strobe signal divider is configured to initialize half of the plurality of internal write data strobe signals to a low level and initializes the other half of the plurality of internal write data strobe signals to a high level.

10. The memory device of claim 1 , wherein the plurality of internal write data strobe signals include a first write data strobe signal, a second write data strobe signal, a third write data strobe signal, and a fourth write data strobe signal respectively corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, and
wherein a frequency of each of the first through fourth internal write data strobe signals is half of a frequency of the write data strobe signal.

11. The memory device of claim 10 , wherein the write data strobe signal divider includes:
a first latch including:
a first input terminal;
a first output terminal outputting a first internal write data strobe signal; and
a second output terminal outputting a third internal write data strobe signal;

a second latch including:
a second input terminal connected with the first output terminal;
a third output terminal outputting a second internal write data strobe signal; and
a fourth output terminal connected with the first input terminal and outputting a fourth internal write data strobe signal,

wherein the first latch is configured to:
output a reset value and a complementary reset value to the first output terminal and the second output terminal based on the reset signal; and
output, to the first output terminal and the second output terminal, a value and a complementary value, respectively, of the fourth internal write data strobe signal input through the first input terminal based on a rising edge of the write data strobe signal; and
wherein the second latch is configured to:
output the reset value and the complementary reset value to the third output terminal and the fourth output terminal based on the reset signal; and
output, to the third output terminal and the fourth output terminal, a value and a complementary value, respectively, of the first internal write data strobe signal input through the second input terminal based on a rising edge of a complementary write data strobe signal.

12. The memory device of claim 1 , wherein the buffer die further includes:
a read data strobe signal transmitter configured to generate a read data strobe signal to be provided to the host device through the first channel based on the plurality of internal write data strobe signals,
wherein the data transceiver is configured to align read data, which are transmitted from the core die that supports the first channel, with toggle timings of the read data strobe signal based on the plurality of internal write data strobe signals to transmit the read data to the host device.

13. The memory device of claim 1 , wherein a frequency of the write data strobe signal is two times a frequency of the clock signal.

14. The memory device of claim 1 , wherein the buffer die includes 128 data pins configured to receive the write data and 8 strobe pins configured to receive the write data strobe signal, the 128 data pins and the 8 strobe pins corresponding to the first channel.

15. A memory device comprising:
a buffer die configured to communicate with a host device through a plurality of channels; and
a first core die stacked on the buffer die, connected to the buffer die through a silicon through electrode and including a first memory cell array corresponding to a first channel of the plurality of channels; and
a second core die stacked on the first core die, connected to the first core die through the silicon through electrode and including a second memory cell array corresponding to the first channel,
wherein the buffer die includes:
a command/address receiver configured to receive a command and a stack identifier provided from the host device to the first channel, based on a clock signal provided from the host device to the first channel;
a control logic circuit configured to generate an internal command based on the command received from the command/address receiver and to generate a re

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Byongmo
• Kim Jihye
• Ryu Je Min
• Kil Beomyong
• Ahn Sungoh

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title