Memory chip and stack type semiconductor apparatus including the same

Patent metadata

Field	Value
Publication number	US-2016358671-A1
Application number	US-201514862446-A
Country	US
Kind code	A1
Filing date	Sep 23, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A memory chip may include a plurality of channels including a plurality of memory banks and having a separate input/output interface, and each of the plurality of channels may be configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that final data output has ended.

First claim

What is claimed is:

1 . A memory chip comprising:
a plurality of memory banks configured to simultaneously output previously stored data according to a read command; a plurality of data compression blocks configured to generate compression data groups by compressing respective unit data groups outputted from the plurality of memory banks; and a test control circuit configured to simultaneously latch the compression data groups and sequentially output latched data as test read data according to a read start signal.

2 . The memory chip according to claim 1 , wherein the test control circuit is configured to sequentially output the latched data according to a repeated order of the plurality of memory banks.

3 . The memory chip according to claim 1 , wherein the test control circuit comprises:
a data processing block configured to simultaneously latch the compression data groups according to a strobe signal and sequentially output the latched data according to a plurality of output control signals; a multiplexing block configured to output the test read data by selecting output signals of the data processing block according to a plurality of bank selection signals; and a control block configured to generate the plurality of output control signals and the plurality of bank selection signals according to the read start signal.

4 . The memory chip according to claim 3 , wherein the data processing block comprises:
data processing units corresponding to a number of the plurality of memory banks, wherein the data processing unit comprises: a plurality of latches configured to simultaneously latch a compression data group corresponding to a corresponding memory bank among the compression data groups according to the strobe signal; a logic gate configured to output a group compression signal by combining signals latched in the plurality of latches; a first multiplexer configured to sequentially select and output the signals, which have been latched in the plurality of latches, according to the plurality of output control signals; and a second multiplexer configured to select and output output of the first multiplexer or the group compression signal outputted from the logic gate according to a group compression enable signal.

5 . The memory chip according to claim 3 , wherein the control block comprises:
a first counter configured to generate the plurality of bank selection signals according to a clock signal; and a second counter configured to generate the plurality of output control signals according to a signal of the plurality of bank selection signals.

6 . A memory chip comprising:
a plurality of channels including a plurality of memory banks and having a separate input/output interface, wherein each of the plurality of channels are configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that a final data output has ended.

7 . The memory chip according to claim 6 , wherein a channel having a highest order of the plurality of channels is configured to perform a data output operation according to the read start signal.

8 . The memory chip according to claim 6 , wherein remaining channels, except for a channel having a highest order of the plurality of channels, are configured to perform a data output operation according to the read end signal of a previous channel.

9 . The memory chip according to claim 6 , wherein the plurality of channels are configured to simultaneously output data stored in the plurality of memory banks according to a read command.

10 . The memory chip according to claim 6 , wherein each of the plurality of channels comprises:
a data processing block configured to simultaneously latch the compression data groups according to a strobe signal and sequentially output latched data according to a plurality of output control signals; a multiplexing block configured to output the test read data by selecting output signals of the data processing block according to a plurality of bank selection signals; and a control block configured to generate the plurality of output control signals, the plurality of bank selection signals, and the read end signal according to the read start signal or the read end signal of a previous channel.

11 . The memory chip according to claim 10 , wherein the data processing block comprises:
data processing units corresponding to a number of the plurality of memory banks, wherein the data processing unit comprises: a plurality of latches configured to simultaneously latch a compression data group corresponding to a corresponding memory bank among the compression data groups according to the strobe signal; a logic gate configured to output a group compression signal by combining signals latched in the plurality of latches; a first multiplexer configured to sequentially select and output the signals, which have been latched in the plurality of latches, according to the plurality of output control signals; and a second multiplexer configured to select and output output of the first multiplexer or the group compression signal outputted from the logic gate according to a group compression enable signal.

12 . The memory chip according to claim 10 , wherein the control block comprises:
a count clock generation unit configured to generate a count clock signal according to the read start signal, the read end signal of the previous channel, and a clock signal; a first counter configured to generate the plurality of bank selection signals according to the count clock signal; and a second counter configured to generate the plurality of output control signals according to a signal of the plurality of bank selection signals.

13 . A stack type semiconductor apparatus comprising:
a plurality of stacked memory chips in which signal input/output is performed, wherein each of the plurality of memory chips includes a plurality of channels including a plurality of memory banks, and are configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks of each of the plurality of channels, sequentially output latched data as test read data according to a read start signal or a read end signal of a previous channel, and generate the read end signal which defines that final data output has ended.

14 . The stack type semiconductor apparatus according to claim 13 , wherein the previous channel includes any one of the plurality of channels in a substantially same memory chip or any one of the plurality of channels of another memory chip.

15 . The stack type semiconductor apparatus according to claim 13 , wherein a channel having a highest order of the plurality of channels of a highest or lowest memory chip of the plurality of memory chips is configured to perform a data output operation according to the read start signal.

16 . The stack type semiconductor apparatus according to claim 13 , wherein remaining channels, except for a channel having a highest order of the plurality of channels of a highest or lowest memory chip of the plurality of memory chips, are configured to perform a data output operation according to the read end signal of the previous channel.

17 . The stack type semiconductor apparatus according to claim 13 , wherein the plurality of memory chips a

Assignees

• Sk Hynix Inc

Inventors

• Lee Dong Uk
• Kim Kyung Whan

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/40 Primary

  using compression techniques · CPC title

• G11C29/28

  Dependent multiple arrays, e.g. multi-bit arrays · CPC title