Semiconductor devices and semiconductor systems including the same

Patent metadata

Field	Value
Publication number	US-2016372173-A1
Application number	US-201514882942-A
Country	US
Kind code	A1
Filing date	Oct 14, 2015
Priority date	Jun 16, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

First claim

1 . A semiconductor device comprising:
a buffer control signal generation circuit configured for generating a buffer control signal which is enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated; an input control signal generation circuit configured for receiving a data strobe signal to generate an input control signal, in response to the buffer control signal; and an internal data generation circuit configured for receiving a data signal to generate internal data, in synchronization with the input control signal.

2 . The semiconductor device of claim 1 , wherein the predetermined section is set to be a period that remains after subtracting a write preamble section from a write latency (WL) section.

3 . The semiconductor device of claim 1 , wherein the buffer control signal generation circuit includes:
a pull-up signal generator configured for generating a pull-up signal in response to the write command signal and an external clock signal; a pull-down signal generator configured for generating a pull-down signal in response to the write command signal; and a buffer control signal output unit configured for driving and outputting the buffer control signal in response to the pull-up signal and the pull-down signal.

4 . The semiconductor device of claim 3 ,
wherein the pull-up signal is enabled in synchronization with a point of time that the predetermined section elapses from a point of time that the write command signal is generated; and wherein the pull-down signal is enabled in synchronization with a point of time that the write command signal is generated.

5 . The semiconductor device of claim 3 , wherein the pull-up signal generator includes:
a command delay unit configured for shifting the write command signal to generate at least two delayed write command signals, in synchronization with the external clock signal; and a selection output unit configured for selecting one of the delayed write command signals to output the selected signal as the pull-up signal, in response to a selection signal.

6 . The semiconductor device of claim 3 , wherein the pull-down signal generator includes:
a level signal generator configured for generating a level signal in synchronization with the write command signal; and a pull-down signal output unit configured for generating the pull-down signal in response to the level signal.

7 . The semiconductor device of claim 3 , wherein the buffer control signal output unit generates and outputs the buffer control signal, the buffer control signal enabled in response to the pull-up signal and disabled in response to the pull-down signal.

8 . The semiconductor device of claim 3 , wherein the buffer control signal output unit includes:
a driver configured for driving an internal node in synchronization with the pull-up signal and the pull-down signal; and a latch unit configured for latching a signal of the internal node to generate the buffer control signal.

9 . The semiconductor device of claim 1 ,
wherein the input control signal generation circuit is configured for receiving first and second data strobe signals to generate first to fourth input control signals, in response to the buffer control signal, wherein the internal data generation circuit is configured for receiving the data signal to generate the internal data, in synchronization with the first to fourth input control signals. and wherein the input control signal generation circuit includes: a data strobe signal buffer configured for buffering the first and second data strobe signals to generate a first internal data strobe signal and a second internal data strobe signal, in response to the buffer control signal; a reset signal generator configured for generating a reset signal, the reset signal enabled in synchronization with a point of time that the predetermined section elapses from a point of time that the write command signal is generated; and a data strobe signal divider configured for dividing the first and second internal data strobe signals to generate the first to fourth input control signals, in response to the reset signal.

10 . The semiconductor device of claim 9 , wherein the reset signal generator includes:
a command delay unit configured for shifting the write command signal to generate two or more delayed write command signals, in synchronization with the external clock signal; and a selection output unit configured for selecting one of delayed write command signals to output the selected signal as the reset signal, in response to a selection signal.

11 . The semiconductor device of claim 9 , wherein the data strobe signal divider includes:
a first divider configured for generating the third and fourth input control signals from the first and second input control signals in synchronization with the first internal data strobe signal; and a second divider configured for generating the first and second input control signals from the third and fourth input control signals in synchronization with the second internal data strobe signal.

12 . The semiconductor device of claim 9 , wherein if the reset signal is enabled, the first and second input control signals are initialized to have opposite phases to each other and the third and fourth input control signals are initialized to have opposite phases to each other.

13 . The semiconductor device of claim 1 ,
wherein the input control signal generation circuit is configured for receiving first and second data strobe signals to generate first to fourth input control signals, in response to the buffer control signal, wherein the internal data generation circuit is configured for receiving the data signal to generate the internal data, in synchronization with the first to fourth input control signals. and wherein the input control signal generation circuit includes: a data strobe signal buffer configured for buffering the first and second data strobe signals to generate a first internal data strobe signal and a second internal data strobe signal, in response to the buffer control signal; a reset signal generator configured for detecting phases of the first and second data strobe signals to generate a reset signal; and a data strobe signal divider configured for dividing the first and second internal data strobe signals to generate the first to fourth input control signals, in response to the reset signal.

14 . The semiconductor device of claim 13 , wherein the reset signal generator generates the reset signal, the reset signal enabled if the first and second data strobe signals have opposite phases to each other.

15 . A semiconductor device comprising:
a reset signal generator configured for generating a reset signal, the reset signal enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated; a first divider configured for generating third and fourth input control signals from first and second input control signals in synchronization with a first internal data strobe signal; and a second divider configured for generating the first and second input control signals from the third and fourth input control signals in synchronization with a second internal data strobe signal.

16 . The semiconductor device of claim of claim 15 , wherein the predetermined section is set to be a period that remains after subtracting a write preamble section from a write latency (WL) section.

17 . The semiconductor devic

Assignees

• Sk Hynix Inc

Inventors

• Kim Min Chang
• Kim Chang Hyun
• Lee Do Yun
• Lee Jae Jin
• Jung Hun Sam

Classifications

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/109

  Control signal input circuits · CPC title