Dynamic generation of ATPG mode signals for testing multipath memory circuit

Patent metadata

Field	Value
Publication number	US-11073553-B2
Application number	US-201816185629-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Dec 29, 2017
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.

First claim

What is claimed is:

1. A circuit, comprising:
a multipath memory having multiple cells; and
a plurality of sequence generators, each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell and comprises a sequence configuration register to configure a timing sequence of the ATPG mode signal to test each cell,
the ATPG mode signal for each cell is configured via a sequence configuration input that controls the timing sequence for testing each cell, wherein the ATPG mode signal for each cell indicates whether test data or functional data is output from the respective cell.

2. The circuit of claim 1 , wherein each cell of the multipath memory includes a memory array, one of the cells includes an error checking and correction (ECC) memory array and another one of the cells includes a data memory array, the ECC memory array stores an ECC bit that corresponds to data that is stored in the data memory array.

3. The circuit of claim 2 , further comprising gate logic that receives data from the ECC memory array and the data memory array to generate output data corresponding to the data in the ECC memory array or the data memory array.

4. The circuit of claim 2 , further comprising an input multiplexer to select between a test interface and a functional interface in response to a test mode signal that varies between test mode and functional mode, wherein the test interface provides test data for the cell via an output of the input multiplexer if the test mode signal is in test mode and the functional interface provides functional data to the memory array via the output of the input multiplexor if the test mode signal is in functional mode.

5. The circuit of claim 4 , further comprising a clocked logic array that is driven from the output of the input multiplexor, the clocked logic array receives the test data for the cell in the test mode.

6. The circuit of claim 5 , further comprising an output multiplexer to select between the clocked logic array and the memory array in response to the ATPG mode signal, the ATPG mode signal causes the output multiplexer to provide clocked logic array output from the cell in test mode and to provide memory array output from the cell in functional mode.

7. The circuit of claim 1 , wherein the timing sequence includes a number of test pulses and a pulse width for the test pulses of the ATPG mode signal to test each cell.

8. The circuit of claim 1 , wherein the sequence generator further comprises a sequence shift register to generate the timing sequence, the sequence shift register is loaded in response to a scan enable signal that loads the contents of the sequence configuration register into the sequence shift register.

9. The circuit of claim 8 , wherein the sequence generator further comprises a multiplexer to drive the ATPG mode signal, the multiplexer selects between the sequence shift register and a default ATPG signal based on an override select signal.

10. A circuit, comprising:
a multipath memory having multiple cells; and
a plurality of sequence generators, each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell,
the ATPG mode signal for each cell is configured via a sequence configuration input that controls a number of test pulses and a pulse width for the test pulses to test each cell,
each cell of the multipath memory includes:
a memory array to store functional data for the cell;
an input multiplexer to select between a test interface and a functional interface in response to a test mode signal that varies between test mode and functional mode, the test interface provides test data for the cell via an output of the input multiplexer if the test mode signal is in test mode and the functional interface provides functional data to the memory array via the output of the input multiplexor if the test mode signal is in functional mode;
a clocked logic array that is driven from the output of the input multiplexor, the clocked logic array receives the test data for the cell in the test mode; and
an output multiplexer to select between the clocked logic array and the memory array in response to the ATPG mode signal, the ATPG mode signal causes the output multiplexer to provide clocked logic array output from the cell in test mode and to provide memory array output from the cell in functional mode.

11. The circuit of claim 10 , wherein one of the cells of the multipath memory includes an error checking and correction (ECC) memory array and another one of the cells includes a data memory array, the ECC memory array stores an ECC bit that corresponds to data that is stored in the data memory array.

12. The circuit of claim 11 , further comprising gate logic that receives data from the ECC memory array and the data memory array to generate output data corresponding to the data in the ECC memory array or the data memory array.

13. The circuit of claim 10 , wherein the sequence generator further comprises a sequence configuration register to configure the number of test pulses and the pulse width for the test pulses of the ATPG mode signal to test each cell.

14. The circuit of claim 13 , wherein the sequence generator further comprises a sequence shift register to generate the number of test pulses and the pulse width for the test pulses, the sequence shift register is loaded in response to a scan enable signal that loads the contents of the sequence configuration register into the sequence shift register.

15. The circuit of claim 14 , wherein the sequence generator further comprises a multiplexer to drive the ATPG mode signal, the multiplexer selects between the sequence shift register and a default ATPG signal based on an override select signal.

16. A method, comprising:
receiving a sequence configuration pattern signal that indicates a number of test pulses to test a multipath memory and a timing sequence;
generating an automatic test pattern generator (ATPG) mode signal for a call, the ATPG mode signal having the number of test pulses and the timing sequence indicated by the sequence configuration pattern and the ATPG mode signal indicates whether test data or functional data is output from a cell; and
selecting between a clocked logic array that receives the test data and a memory array that receives the functional data in response to the ATPG mode signal, the ATPG mode signal causes output from the clocked logic array to be routed from the multipath memory in test mode and the memory array output to be routed from the multipath memory in functional mode.

17. The method of claim 16 , wherein the multipath memory includes an error checking and correction (ECC) memory array and a data memory array, the ECC memory array stores an ECC bit that corresponds to data that is stored in the data memory array.

18. The method of claim 17 , further comprising selecting between a test interface and a functional interface in response to a test mode signal that varies between test mode and functional mode, wherein the test interface provides test data for the multipath memory if the test mode signal is in test mode and the functional interface provides functional data to the memory array if the test mode signal is in functional mode.

Assignees

• Texas Instruments Inc

Inventors

• Pradeep Wilson
• Narayanan Prakash

Classifications

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title