Bypass system and method that mimics clock to data memory read timing

Patent metadata

Field	Value
Publication number	US-9263100-B2
Application number	US-201314093123-A
Country	US
Kind code	B2
Filing date	Nov 29, 2013
Priority date	Nov 29, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

First claim

The invention claimed is:

1. A bypass system for a memory system comprising: a self-timing circuit and a sense amplifier having a differential input, wherein the self-timing circuit, after being prompted, initiates the sense amplifier after a predetermined time period to evaluate the differential input of the sense amplifier; and wherein said bypass system further comprises:
a memory controller that is configured to provide a bypass enable when a bypass read operation is indicated;
a bypass latch that, when enabled by said bypass enable, latches an input data value, converts said input data value into a corresponding input complementary pair, and provides said input complementary pair to the differential input of the sense amplifier; and
wherein the sense amplifier, when initiated, evaluates said input complementary pair after the predetermined time period and provides an evaluated output data value indicative of said input data value.

2. The bypass system of claim 1 , wherein said memory controller is further configured to prompt the self-timing circuit and to disable normal read control when the bypass read operation is indicated.

3. The bypass system of claim 1 , wherein said bypass latch comprises:
an input latch having a data input receiving said input data value, an enable input receiving said bypass enable, and an output providing a corresponding complementary bit pair; and
a data driver that is configured, when enabled, to drive said corresponding complementary bit pair as said input complementary pair to the differential input of the sense amplifier.

4. The bypass system of claim 3 , wherein the memory system comprises a multiport register file with separate read and write domains, and wherein said memory controller comprises:
a read controller providing a first read clock to a clock input of said input latch and providing an internal clock for activating the self-timing circuit; and
a local controller for incorporating the self-timing circuit for receiving said internal clock, wherein said local controller provides a driver enable signal to an enable input of said data driver.

5. The bypass system of claim 4 , wherein said read controller receives a bypass indication signal and a second read clock, wherein said read controller asserts said first read clock and said internal clock synchronous with said second read clock signal when said bypass read operation is indicated.

6. The bypass system of claim 3 , wherein the memory system includes a memory array, further comprising:
an access interface for providing bit line information from the memory array to the differential input of the sense amplifier; and
wherein said local controller provides an access enable signal to an enable input of said access interface.

7. The bypass system of claim 1 , further comprising a self test circuit that controls providing said input data value to said bypass latch and that provides a memory read bypass signal to said memory controller to indicate said bypass read operation.

8. A method of performing a bypass read operation that mimics timing of a memory system, comprising:
receiving a bypass enable indicative of the bypass read operation;
disabling a normal read operation of the memory system when the bypass read operation is indicated;
converting an input data value to an input complementary pair when the bypass read operation is indicated;
providing the input complementary pair to a differential input of a sense amplifier of the memory system;
initiating a self-timing circuit of the memory system after the bypass read operation is indicated, wherein the self-timing circuit activates the sense amplifier after a predetermined time period; and
converting, by the sense amplifier upon activation, the input complementary pair to an output data value.

9. The method of claim 8 , further comprising:
providing the input data value to a data input of the memory system; and
providing the bypass enable, by a self test circuit, to initiate the bypass read operation.

10. The method of claim 8 , further comprising latching the output data value into a register.

11. The method of claim 8 , wherein said disabling a normal read operation includes disabling access logic having an input coupled to a memory array of the memory system and an output coupled to the differential input of the sense amplifier.

12. The method of claim 8 , wherein said converting an input data value to an input complementary pair comprises:
enabling a latch having an input receiving the input data value when the bypass read operation is indicated; and
latching, by the latch after being enabled, the input data value to the input complementary pair.

13. The method of claim 12 , wherein said providing the input complementary pair to a differential input of a sense amplifier comprises enabling a driver having an input coupled to an output of the latch and having an output coupled to the differential input of the sense amplifier.

14. The method of claim 12 , further comprising clocking the latch synchronous with a read clock of the memory system.

15. The method of claim 8 , wherein said initiating a self-timing circuit of the memory system comprises providing an internal clock synchronous with a read clock of the memory system to initiate the self-timing circuit.

16. A memory system with a bypass system, comprising:
a memory controller that provides a bypass enable and a bypass read signal in response to a bypass read indication, and that provides at least one disable signal to disable a normal read operation in response to said bypass read indication;
a bypass latch that, when enabled by said bypass enable, latches and converts an input data value into a corresponding input complementary pair;
a self-timing circuit that provides a sense signal upon expiration of a predetermined time period that starts when said bypass read signal is provided; and
a sense amplifier that evaluates said input complementary pair provided by said bypass latch when initiated by said sense signal and that provides an evaluated output data value indicative of said input data value.

17. The memory system of claim 16 , wherein said bypass latch comprises:
an input latch having a data input receiving said input data value, an enable input receiving said bypass enable, and an output providing a corresponding complementary bit pair when said bypass enable is provided; and
a data driver that drives said corresponding complementary bit pair as said input complementary pair to a differential pair input of said sense amplifier.

18. The memory system of claim 17 , wherein said memory controller provides a driver enable signal to an enable input of said data driver in response to said bypass read signal being provided.

19. The memory system of claim 16 , further comprising:
an access interface having an output providing a differential bit pair from a memory array to a differential input pair of said sense amplifier when said output is enabled during a read operation; and
wherein said at least one disable signal provided by said memory controller disables said output of said access interface in response to said bypass read signal being provided.

20. The memory system of claim 16 , further comprising a self test circuit that controls providing said input data value to said bypass latch and that provides said bypass read indication to said memory controller to disable said normal read operation and to initiate a bypass read operation.

Assignees

• Freescale Semiconductor Inc

Inventors

• Garni Bradley J
• Pham Huy Van V
• Starnes Glenn E
• Jetton Mark
• Liston Thomas W

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C29/50012 Primary

  of timing · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title