Built-in self test circuit for segmented static random access memory (SRAM) array input/output
US-12584961-B2 · Mar 24, 2026 · US
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Kumar Tanuj patents
Kumar Tanuj is listed as an inventor on 16 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Tanuj |
| Total patents | 16 |
| First publication | Mar 26, 2020 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
At-speed transition fault testing for a multi-port and multi-clock memory
US-2026018228-A1 · Jan 15, 2026 · US
Optical Sensing of Crop Processing Components of Harvester
US-2026007097-A1 · Jan 8, 2026 · US
At-speed transition fault testing for a multi-port and multi-clock memory
US-12437825-B2 · Oct 7, 2025 · US
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
US-12353341-B2 · Jul 8, 2025 · US
Built-in self test circuit for segmented static random access memory (sram) array input/output
US-2025069678-A1 · Feb 27, 2025 · US
Thread-Based Transistors
US-2024431123-A1 · Dec 26, 2024 · US
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
US-12170120-B2 · Dec 17, 2024 · US
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
US-2024143239-A1 · May 2, 2024 · US
At-speed transition fault testing for a multi-port and multi-clock memory
US-2024112748-A1 · Apr 4, 2024 · US
Recent patents
Latest publications not already listed above.
Built-in self test circuit for segmented static random access memory (sram) array input/output
US-2024071546-A1 · Feb 29, 2024 · US
Built-in self test circuit for segmented static random access memory (sram) array input/output
US-2024069096-A1 · Feb 29, 2024 · US
Circuit and method for at speed detection of a word line fault condition in a memory circuit
US-11393532-B2 · Jul 19, 2022 · US
Circuit for detection of single bit upsets in generation of internal clock for memory
US-11025252-B2 · Jun 1, 2021 · US
Circuit and method for at speed detection of a word line fault condition in a memory circuit
US-2020342940-A1 · Oct 29, 2020 · US
Circuit for detection of single bit upsets in generation of internal clock for memory
US-2020099378-A1 · Mar 26, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| St Microelectronics Int Nv | 14 |
| Tufts College | 1 |
| Deere & Co | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C2029/1204 | 10 |
| G11C29/1201 | 8 |
| G11C2029/1202 | 7 |
| G11C29/36 | 5 |
| G11C29/022 | 5 |