Methods for improving wafer planarity and bonded wafer assemblies made from the methods

Patent metadata

Field	Value
Publication number	US-9978582-B2
Application number	US-201615379759-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Dec 16, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO 2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

First claim

What is claimed is:

1. A semiconductor wafer comprising:
a semiconductor wafer having a first surface and a second surface; and
at least one strain-modifying layer on the second surface inducing a compressive force, tensile force or compressive and tensile forces on the second surface to reduce a warp or bow of the semiconductor wafer before the at least one strain-modifying layer is applied;
wherein the at least one strain-modifying layer comprises first and second strain-modifying layers;
wherein the first strain-modifying layer is patterned to form a plurality of elongated layer segments extending in a first direction on the semiconductor wafer, and the second strain-modifying layer is patterned to form a plurality of elongated layer segments extending in a second direction on the semiconductor wafer;
wherein the first strain-modifying layer applies a compressive force on the second surface and the second strain-modifying layer applies a tensile force on the second surface.

2. The semiconductor wafer of claim 1 wherein the at least one strain-modifying layer is selected from the group consisting of SiO 2 , silicon nitride, a metal oxide material or a group III-nitride.

3. The semiconductor wafer of claim 1 wherein the semiconductor wafer is a GaN on sapphire wafer, substrate or template, and the strain modifying layer is an SiO 2 layer.

4. The semiconductor wafer of claim 1 , wherein the first strain-modifying layer and the second strain-modifying layer are of the same or different layer materials.

5. The semiconductor wafer of claim 1 , wherein:
the plurality of elongated layer segments extending in the first direction are formed by patterning the first strain-modifying layer with a first predetermined strain-modifying layer pattern and selectively removing predetermined portions of the first strain-modifying layer, and
the plurality of elongated layer segments extending in the second direction are formed by patterning the second strain-modifying layer with a second predetermined strain-modifying layer pattern and selectively removing predetermined portions of the second strain-modifying layer.

6. The semiconductor wafer of claim 1 , wherein areas covered by the plurality of elongated layer segments extending in the first direction and the plurality of elongated layer segments extending in the second direction are approximately two-thirds of the area of the semiconductor wafer.

7. The semiconductor wafer of claim 1 , wherein thickness of the at least one strain-modifying layer is determined based at least in part on the warp or bow measured across a surface of the semiconductor wafer.

8. The semiconductor wafer of claim 7 , wherein the at least one strain-modifying layer has a thickness of 1 μm per each about 5 μm to 8 μm of warp or bow.

9. The semiconductor wafer of claim 1 , wherein the at least one strain-modifying layer is deposited on the second surface in a plasma-enhanced chemical vapor deposition (PECVD) process.

10. The semiconductor wafer of claim 1 , wherein the at least one strain-modifying layer is deposited on the second surface in a physical vapor deposition process.

11. A method of reducing warp or bow in a semiconductor wafer comprising:
providing a semiconductor wafer having a first surface and a second surface; and
depositing at least one strain-modifying layer on the second surface inducing a compressive force, tensile force or compressive and tensile forces on the second surface to reduce a warp or bow of the semiconductor wafer before the at least one strain-modifying layer is applied;
wherein the at least one strain-modifying layer comprises first and second strain-modifying layers;
wherein the first strain-modifying layer is patterned to form a plurality of elongated layer segments extending in a first direction on the semiconductor wafer, and the second strain-modifying layer is patterned to form a plurality of elongated layer segments extending in a second direction on the semiconductor wafer;
wherein the first strain-modifying layer applies a compressive force on the second surface and the second strain-modifying layer applies a tensile force on the second surface.

12. The method of claim 11 , wherein the at least one strain-modifying layer is selected from the group consisting of SiO 2 , silicon nitride, a metal oxide material or a group III-nitride.

13. The method of claim 11 , wherein the semiconductor wafer is a GaN on sapphire wafer, substrate or template, and the strain modifying layer is an SiO 2 layer.

14. The method of claim 11 , wherein the first strain-modifying layer and the second strain-modifying layer are of the same or different layer materials.

15. The method of claim 11 , wherein:
the plurality of elongated layer segments extending in the first direction are formed by patterning the first strain-modifying layer with a first predetermined strain-modifying layer pattern and selectively removing predetermined portions of the first strain-modifying layer, and
the plurality of elongated layer segments extending in the second direction are formed by patterning the second strain-modifying layer with a second predetermined strain-modifying layer pattern and selectively removing predetermined portions of the second strain-modifying layer.

16. The method of claim 11 , wherein areas covered by the plurality of elongated layer segments extending in the first direction and the plurality of elongated layer segments extending in the second direction are approximately two-thirds of the area of the semiconductor wafer.

17. The method of claim 11 , further comprising:
measuring the warp or bow across a surface of the semiconductor wafer; and
determining thickness of the at least one strain-modifying layer based at least in part on the measured warp or bow.

18. The method of claim 17 , wherein the at least one strain-modifying layer has a thickness of 1 μm per each about 5 μm to 8 μm of warp or bow.

19. The method of claim 11 , wherein the at least one strain-modifying layer is deposited on the second surface in a plasma-enhanced chemical vapor deposition (PECVD) process.

20. The method of claim 11 , wherein the at least one strain-modifying layer is deposited on the second surface in a physical vapor deposition process.

Assignees

• Ostendo Technologies Inc

Inventors

• Batinica Gregory
• Yadavalli Kameshwar
• Fan Qian
• Haskell Benjamin A
• El-Ghoroury Hussein S

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W72/07236

  Soldering or alloying · CPC title