Integrated circuit device including N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel metal-oxide semiconductor (PMOS) transistor region

Patent metadata

Field	Value
Publication number	US-12433017-B2
Application number	US-202418746928-A
Country	US
Kind code	B2
Filing date	Jun 18, 2024
Priority date	Dec 2, 2020
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate including a first device region and a second device region;
at least one first channel region extending in a first horizontal direction on the first device region;
at least one second channel region extending in the first horizontal direction on the second device region;
an isolation film covering opposite side walls of each of the at least one first channel region and the at least one second channel region;
a first gate cut insulating pattern on the isolation film on the first device region;
a second gate cut insulating pattern on the isolation film on the second device region;
a gate line extending on the first device region and the second device region in a second horizontal direction that crosses the first horizontal direction, the gate line having a length in the second horizontal direction limited by the first gate cut insulating pattern and the second gate cut insulating pattern, each of the at least one first channel region and the at least one second channel region being surrounded by the gate line; and
an inter-region insulating pattern on the isolation film between the at least one first channel region and the at least one second channel region, the inter-region insulating pattern partially penetrating the gate line in a vertical direction,
wherein the inter-region insulating pattern has a sidewall linearly extended in the vertical direction without a stepped portion.

2. The integrated circuit device as claimed in claim 1 , wherein the inter-region insulating pattern has a local surface planarly extended, the local surface facing the gate line.

3. The integrated circuit device as claimed in claim 1 , wherein the inter-region insulating pattern has a non-planar surface facing the gate line.

4. The integrated circuit device as claimed in claim 1 , wherein the isolation film has different shapes in the first device region and the second device region.

5. The integrated circuit device as claimed in claim 1 , wherein the inter-region insulating pattern has a bottom surface facing the substrate, the bottom surface being in contact with the isolation film.

6. The integrated circuit device as claimed in claim 1 , wherein the inter-region insulating pattern has a first sidewall and a second sidewall that are opposite to each other in the second horizontal direction, the first sidewall facing the at least one first channel region in the second horizontal direction, and the second sidewall facing the at least one second channel region in the second horizontal direction.

7. The integrated circuit device as claimed in claim 1 , wherein the at least one first channel region has a first topmost surface distal to the substrate, the at least one second channel region has a second topmost surface distal to the substrate, and the inter-region insulating pattern has a third topmost surface distal to the substrate, and
wherein a level of each of the first topmost surface, the second topmost surface, and the third topmost surface is lower than a level of a topmost surface of the gate line.

8. The integrated circuit device as claimed in claim 1 , wherein the inter-region insulating pattern has a top surface distal to the substrate, the top surface being a non-planar surface.

9. The integrated circuit device as claimed in claim 1 , wherein:
the gate line includes:
a first portion covering the at least one first channel region on the first device region and having a first stack structure,
a second portion covering the at least one second channel region on the second device region and having a second stack structure that is different from the first stack structure, and
a gate connecting portion integrally connected to the first portion and the second portion and covering a top surface of the inter-region insulating pattern, and
the gate connecting portion has a structure different from the first stack structure and the second stack structure.

10. The integrated circuit device as claimed in claim 1 , wherein:
the gate line includes a first gate portion on the first device region and a second gate portion on the second device region, and
the first gate portion is separated from the second gate portion with the inter-region insulating pattern between the first gate portion and the second gate portion in the second horizontal direction.

11. The integrated circuit device as claimed in claim 1 , wherein each of the first gate cut insulating pattern and the second gate cut insulating pattern has a bottom surface facing the substrate, the bottom surface being in contact with the isolation film.

12. An integrated circuit device, comprising:
a substrate including a first device region and a second device region separated from the first device region;
at least one first fin active region extending in a first horizontal direction on the first device region;
at least one second fin active region extending in the first horizontal direction on the second device region;
an isolation film covering opposite side walls of each of the at least one first fin active region and the at least one second fin active region;
a gate line extending on the first device region and the second device region in a second horizontal direction that crosses the first horizontal direction;
at least one first channel region on the at least one first fin active region, the at least one first channel region surrounded by the gate line;
at least one second channel region on the at least one second fin active region, the at least one second channel region surrounded by the gate line; and
an inter-region insulating pattern on the isolation film between the at least one first channel region and the at least one second channel region, the inter-region insulating pattern partially penetrating the gate line in a vertical direction,
wherein the inter-region insulating pattern has a sidewall linearly extended in the vertical direction without a stepped portion.

13. The integrated circuit device as claimed in claim 12 , wherein the inter-region insulating pattern has a local surface planarly extended, the local surface facing the gate line.

14. The integrated circuit device as claimed in claim 12 , wherein the inter-region insulating pattern has a non-planar surface facing the gate line.

15. The integrated circuit device as claimed in claim 12 , wherein the isolation film has different shapes in the first device region and the second device region.

16. The integrated circuit device as claimed in claim 12 , wherein each of the at least one first fin active region and the at least one second fin active region has a width in the second horizontal direction, the width gradually decreasing as the distance from the substrate increases along the vertical direction.

17. The integrated circuit device as claimed in claim 12 , wherein the inter-region insulating pattern has a bottom surface facing the substrate, the bottom surface being in contact with the isolation film.

18. The integrated circuit device as claimed in claim 12 , wherein the at least one first channel region has a first topmost surface distal to the substrate, the at least one second channel region has a second topmost surface distal to the substrate, and the inter-region insulating pattern has a third topmost surface distal to the substrate, and
wherein a level of each of the first topmost surface, the second topmost surface, and the third topmost surface is lower than a level of a topmost surface of the gate line.

19. The integrated circuit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Junggil
• Kim Minju
• Koh Donghyi

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title